Chunghwa Picture Tubes, Ltd.

Yen-Yu Huang

Hsi-Ming Chang

Chin-Hai Huang

Chi-Chung Tsai

En-Chih Liu

Szu-Chi Huang

Ya-Ju Lu

Shin-Chuan Chiang

Yu-Hsien Chen

Ying-Hui Chen

Yi-Kai Chen

Shang-Jung Yang

Chieh-Wei Feng

Kune-Yu Lai

An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.

Active device array substrate and manufacturing method thereof

A processing method of a substrate is provided. The substrate is processed by a substrate processing apparatus. The substrate processing apparatus includes a reaction chamber and a secondary chamber surrounding the reaction chamber. The processing method includes: placing the substrate in the reaction chamber; performing a process to increase a pressure in the reaction chamber and a pressure in the secondary chamber, such that the pressure in the secondary chamber is between an atmospheric pressure and the pressure in the reaction chamber; increasing a temperature in the reaction chamber; and processing the substrate by a supercritical fluid in the reaction chamber.

Method for processing substrate

A method for manufacturing a pixel structure is provided. A patterned semiconductor material layer, an insulation material layer, and a gate electrode material layer are formed in sequence on a substrate to form a stacked structure. A patterned photoresist layer is formed on the stacked structure by using a photomask. A portion of the stacked structure is removed to pattern the patterned semiconductor material layer into a patterned semiconductor layer by using the patterned photoresist layer as a mask. Another portion of the stacked structure is etched by using a portion of the patterned photoresist layer as a mask until a portion of the semiconductor layer in the stacked structure is exposed. Then, an exposed portion of the semiconductor layer is modified to increase a conductivity of the exposed portion of the semiconductor layer. Finally, the patterned photoresist layer is removed. A pixel structure manufactured by the method is provided.

Pixel structure

A method of manufacturing a pixel structure is provided. A gate and a gate insulating layer are formed on a substrate. A channel layer is formed on the gate insulating layer, and the material of the channel layer includes a first metal oxide semiconductor material. A source and a drain are formed on opposite sides of the channel layer. An insulating layer has an opening exposing the drain. First and second transparent electrode material layers are formed on the substrate sequentially, the material of the first transparent electrode material layer includes a second metal oxide semiconductor material, and the material of the second transparent electrode material layer includes a metal oxide conductive material. The first and second transparent electrode material layers are patterned using the same mask to form first and second transparent electrode layers, wherein the first transparent electrode layer is in contact with the drain through the opening.

Method of manufacturing pixel structure

A pixel array includes a plurality of pixels. Each pixel has a first sub-pixel, a second sub-pixel, and a pair of third sub-pixels. The first sub-pixel of each pixel and the first sub-pixels of three adjacent pixels are arranged in a two by two array, the second sub-pixel of each pixel and the second sub-pixels of three adjacent pixels are arranged in a two by two array, and one of each of the third sub-pixels of each pixel and one of the third sub-pixels of three adjacent pixels are arranged in a two by two array. A scan line is connected to a switch unit of each of the sub-pixels in a pixel.

Method of driving dual pixel of active matrix organic lighting emitting diode display

A display panel including a pixel array and a gate driver circuit is provided. The pixel array has a plurality of pixels. The gate driver circuit is used for providing a plurality of gate signals to the pixels and includes a plurality of shift registers and a plurality of demultiplexers. The shift registers respectively receive a first gate signal of the gate signals and a first clock signal of a plurality of clock signals to respectively provide a first control signal and a second control signal. The demultiplexers respectively receive a plurality of second clock signals of the clock signals, respectively turn-on according to the first control signal provided by the corresponding one of the shift registers, and respectively cut-off according to the second control signal provided by the corresponding one of the shift registers.

Display panel

Pixel array of active matrix organic lighting emitting diode display, method of driving the same, and method of driving dual pixel of active matrix organic lighting emitting diode display

The manufacturing method of the thin film transistor includes the following steps. A gate, a first insulating layer, a second insulating layer, a metal oxide semiconductor layer, a first etching stop layer, a second etching stop layer and a photoresist structure are sequentially formed. The second etching stop layer, the first etching stop layer, and the metal oxide semiconductor layer are patterned using the photoresist structure as a mask to form a pre-second etching stop pattern, a pre-first etching stop pattern, and a metal oxide semiconductor pattern. The pre-second etching stop pattern and the pre-first etching stop pattern are patterned using the remaining thick portion of the photoresist structure as a mask to form a second etching stop pattern and a first etching stop pattern, and a portion of the second insulating layer is removed to form an insulating pattern. A source and a drain are formed.

Thin film transistor and manufacturing method thereof

A thin film transistor disposed on a substrate, includes a gate, a gate insulation layer, a first source/drain, a semiconductor layer and a second source/drain. The gate is disposed on the substrate. The gate insulation layer covers the gate and the substrate. The first source/drain is disposed on the gate insulation layer. The semiconductor layer is disposed above the gate, extends from the gate insulation layer to the first source/drain, and includes a first portion disposed on the first source/drain and a second portion connected to the first portion. An electrical conductivity of the first portion is higher than that of the second portion. The second source/drain covers and is in contact with the second portion. A manufacturing method of thin film transistor is further provided.

Thin film transistor

A gate driving circuit is provided. The gate driving circuit includes a plurality of gate driving units sequentially coupled to each other. Each of the gate driving units includes a shift register and a de-multiplexer. The shift register receives a start pulse signal, and generates a first control signal and a second control signal according to the start pulse signal and a scan controlling signal, where when the shift register converts the first control signal into the second control signal, the shift register pulls down a voltage level of the first control signal according to the second control signal. The de-multiplexer receives a part of a plurality of clock signals for generating a plurality of gate signals sequentially according to the first control signal, where the clock signals are enabled sequentially, and enable periods of two sequential clock signals are partially overlapped with each other.

Gate driving circuit

A thin film transistor disposed on a substrate is provided. The thin film transistor includes a channel, a gate, a source, a drain and an etching stop layer. The channel is disposed above the substrate and is located between the etching stop layer and the source. The gate is disposed on the substrate and overlapped with the channel. The source is disposed between the channel and the substrate and electrically connected to the channel. The channel is disposed between the drain and the substrate. The etching stop layer is disposed between the drain and the channel and has a first through hole exposing a portion of the channel. The drain is filled in the first through hole of the etching stop layer and is electrically connected to the channel. The drain covers the channel completely.

A double thin film transistor includes a first semiconductor layer, a gate, a second semiconductor layer, a first insulating layer, a second insulating layer, a first source, a first drain, a second source and a second drain. The first semiconductor layer is disposed over a substrate. The gate is disposed over the first semiconductor layer. The second semiconductor layer is disposed over the gate, and the first and second semiconductor layers are the same conductive type. The first insulating layer is disposed between the first semiconductor layer and the gate. The second insulating layer is disposed between the gate and the second semiconductor layer. The first source and the first drain are disposed between the substrate and the second insulating layer. The second source and the second drain are disposed over the second insulating layer.

Double thin film transistor structure with shared gate

The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance.

A thin film transistor including a gate, a channel, a stopper layer, a source and a drain is provided. The channel and the gate are overlapped. The stopper layer covers a portion of the channel and has a ring-shape hole exposing two opposite connecting portions of the channel. A portion of the stopper layer is disposed between the source and the channel and between the drain and the channel. The source and the drain are filled in the ring-shape hole of the stopper layer and electrically connected to the connecting portions of the channel. Moreover, a pixel structure including the thin film transistor is provided.

Growing community of inventors

Taoyuan, Taiwan

Yen-Yu Huang