Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Mediatek Corporation

Asustek Computer Inc.

Siliconware Precision Industries Co., Ltd.

Ambarella International LP

Shin Fang Plastic Industrial Co., Ltd.

Other

National Taiwan University

Hiwin Mikrosystem Corporation

Atomic Energy Council

Destiny Racing (huaian) International Co., Ltd.

Yen-Yu Chen

Chung-Liang Cheng

Wen-Hao Cheng

Yi-Ming Dai

Hsuan-Chih Chu

Wei Zhang

Chun-Chih Lin

Shih Wei Bih

Tze-Liang Lee

Wei-Jen Chen

Chang-Sheng Lee

Jr-Hung Li

Chih-Cheng Liu

Yi-Chen Kuo

Chi-Yuan Shih

Chia-Hsi Wang

Chi-Ming Yang

Ming-Hui Weng

Yahru Cheng

Ching-Yu Chang

Chih-Wei Lin

Jia-Lin Wei

Jen-Cheng Liu

Clement Hsingjen Wann

Ling-Yen Yeh

Shih-Hsun Chang

Chih-Pin Tsao

Wei Chuang Wu

Sheng-Wei Yeh

Chi-Wen Liu

Kuo-Shu Tseng

Yu-Chi Lu

Feng-Chi Hung

Shyh-Fann Ting

Yen-Ting Chiang

Fang-Ting Kuo

Anhao Cheng

Wei-Chen Liao

Chien-Hsun Pan

Dun-Nian Yaung

Ching-Chun Wang

Jhy-Jyi Sze

Hsiao-Hui Tseng

Ming-Hsien Lin

Yao-Yuan Shang

Wen Han Hung

Chih-Kuan Yu

Tung-Huang Chen

Wei-Chun Hua

Chinyu Su

Che-Chih Hsu

Chia Ching Liao

Yi-Chen Chiang

Tsang-Yang Liu

Kuo-Cheng Ching

Teng-Chun Tsai

Shi Ning Ju

Wen-Chun Wang

Chun-Yuan Chen

Chen-Yu Liu

Ching-Hung Kao

Chih-Hsien Lin

Kuo-Yin Lin

Hsiang-Pi Chang

Chia-Chu Lai

Chi-Yuan Chen

Han-Wen Liao

Ho-Chuan Lin

Tzy-Kuang Lee

Hongfa Luan

Soon-Kang Huang

Wan-Chun Pan

Hung-Yao Chen

You-Feng Chen

Chien-Hao Tseng

Ping-Hai Hsu

Po-An Chen

Tzu-Hsuan Hsu

Yu-Wen Liao

Cheng-Yi Peng

Chee-Wee Liu

Shiang-Bau Wang

Chia-Ming Tsai

Hsin-Hung Lee

Wei Chih Chen

Yu-Min Chang

Yueh-Ching Pai

Shao-Yi Chien

Pei-Yu Chou

Meng-Ku Chen

Min-Han Chuang

San-Feng Lin

Ming-Fan Tsai

Chee Wee Liu

Yung-Haw Liaw

Bo-Shiang Fang

Chi-Fong Ai

Ke-Chih Liu

Tung-Li Lee

Yu Chia Chen

A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern

In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Vertical gate field effect transistor

A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.

Gate structures for semiconductor devices

Semiconductor processing apparatuses and methods are provided in which a pre-clean chamber receives a semiconductor wafer from a metal gate layer deposition chamber and at least partially removes an oxide layer on a metal gate layer. In some embodiments, a semiconductor processing apparatus includes a plurality of metal gate layer deposition chambers. Each of the metal gate layer deposition chambers is configured to form a metal gate layer on a semiconductor wafer. At least one pre-clean chamber of the apparatus is configured to receive the semiconductor wafer from one of the metal gate layer deposition chamber and at least partially remove an oxide layer on the metal gate layer.

Apparatus and method for manufacturing metal gate structures

A semiconductor device includes a first cobalt-containing plug disposed over a substrate, a second cobalt-containing plug disposed over the first cobalt-containing plug, a first barrier layer over sidewalls of the second cobalt-containing plug, a second barrier layer over sidewalls of the first barrier layer, and a dielectric layer surrounding the second barrier layer. The first barrier layer contains a metal element. The first and second barrier layers include different material compositions.

Dual metal via for contact resistance reduction

A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

Photoresist layer outgassing prevention

Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Threshold voltage tuning for fin-based integrated circuit device

A method is provided. The method includes the following steps: introducing a first physical vapor deposition (PVD) target and a second PVD target in a PVD system, the first PVD target containing a boron-containing cobalt iron alloy (FeCoB) with an initial boron concentration, and the second PVD target containing boron; determining parameters of the PVD system based on a target boron concentration larger than the initial boron concentration; and depositing a FeCoB film on a substrate according to the parameters of the PVD system.

In situ and tunable deposition of a film

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Partial metal grain size control to improve CMP loading effect

A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Resistive memory cell using an interfacial transition metal compound layer and method of forming the same

A thin-film deposition system includes a thin-film deposition chamber. A magnetron assembly is positioned within the thin-film deposition chamber to assist in thin-film deposition processes. A magnetic sensor apparatus is positioned adjacent to the magnetron assembly. The magnetic sensor apparatus includes a plurality of magnetic sensors that each sense the magnetic field in a particular location within the thin-film deposition chamber. The control system generates a magnetic field distribution based on the sensor signals from the magnetic sensors. An analysis model that has been trained with a machine learning process analyzes the magnetic field distribution and determines whether or not an abnormal magnetic field distributions process. The control system can stop the thin-film deposition process based on the output of the analysis model.

System and method for measuring magnetic fields in PVD system

Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

Redistribution layer features

The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

Multi-functional shutter disk for thin film deposition chamber

A method includes supporting a workpiece on a workpiece holder within a material deposition chamber. The method includes rotating the workpiece holder, tilting the workpiece holder in response to an output of a determination circuit, and controlling a temperature of the workpiece utilizing a heater on a surface of the workpiece holder. The method includes depositing a material on the workpiece. The heater includes first/second/third heating coils. The first heating coil has first/second ends and the first heating coil continuously extends between the first end and the second end. The second heating coil extends between the first/second ends of the first heating coil. The third heating coil extends between the first/second ends of the first heating coil. By using the tunable heating feature and the tilting feature of the workpiece pedestal, the present disclosure can reduce or eliminate the shadowing effect problem of the related workpiece pedestal in the art.

Method for depositing target material in deposition chamber with tiltable workpiece holder

A deposition system is provided capable of cleaning itself by removing a target material deposited on a surface of a collimator. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, a target enclosing the substrate process chamber, and a collimator having a plurality of hollow structures disposed between the target and the substrate, a vibration generating unit, and cleaning gas outlet.

Deposition system and method

Growing community of inventors

Taichung, Taiwan

Yen-Yu Chen