Taiwan Semiconductor Manufacturing Comp. Ltd.

Yen-Wen Chen

Chun-Ren Cheng

Chi-Yuan Shih

Shih-Fen Huang

Yi-Chuan Teng

You-Ru Lin

Ching-Hui Lin

Yi Heng Tsai

Fu-Chun Huang

Fan Hu

Yan-Jie Liao

Anderson Lin

Felix Ying-Kit Tsui

Wen-Chuan Tai

Hsin-Li Cheng

Kai-Fung Chang

Jyun-Ying Lin

Ting-Chen Hsu

Jing-Hwang Yang

Ivan Hua-Shu Wu

Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device

The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

Reduction of electric field enhanced moisture penetration by metal shielding

Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.

Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high &#x3ba; dielectric material. By using a high &#x3ba; material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

Film scheme for a high density trench capacitor

Growing community of inventors

Hsinchu County, Taiwan

Yen-Wen Chen