Mediatek Corporation

Mstar Semiconductor, Inc.

Yen-Tso Chen

Chih-Ming Hung

Jing-Hong Conan Zhan

Tzu-Chin Lin

Jui-Lin Hsu

Wei-Hsiu Hsu

Jen-Hao Cheng

Hsiang-Yun Chu

Hao-Wei Huang

Song-Yu Yang

Jian-Yu Ding

Kun-Yin Wang

A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.

Semiconductor chip with local oscillator buffer reused for loop-back test and associated loop-back test method

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

Semiconductor chip with local oscillator buffer reused for signal transmission and associated transmission method

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

An oscillator apparatus includes an oscillator core circuit. The oscillator core circuit includes an inverting transconductance amplifier, at least one first capacitor, at least one second capacitor, and a resonator. The at least one first capacitor is connected between an input of the inverting transconductance amplifier and a ground level. The at least one second capacitor is connected between an output of the inverting transconductance amplifier and the ground level. The resonator has a first port connected to the input of the inverting transconductance amplifier and a second port connected to the output of the inverting transconductance amplifier. The first port is decoupled from the second port.

Oscillator scheme capable of reducing far-out phase noise and closed-in phase noise

An oscillator circuit has a reconfigurable oscillator amplifier. The reconfigurable oscillator amplifier is used to be coupled to a resonant circuit in parallel. The reconfigurable oscillator amplifier supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier employs one of the different circuit configurations under one of the different operation modes.

Oscillator circuit with reconfigurable oscillator amplifier and/or hybrid amplitude calibration circuit and associated method

A signal generator and an associated resonator circuit are provided. The signal generator includes the resonator circuit and a core circuit. The resonator circuit further includes a first inductor (L), a second inductor (L), a plurality of capacitors and a switching circuit. The first inductor (L) has a first terminal (N) and a third terminal (N), and the second inductor (L) has a second terminal (N) and a fourth terminal (N). The switching circuit includes a first switch (S), a second switch (S), a third switch (S) and a fourth switch (S). The core circuit further includes a first inner circuit, a first outer circuit, a second inner circuit, and a second outer circuit. Configurations of these switches are adjustable and resonance caused between these terminals is changed accordingly.

Signal generator and associated resonator circuit

A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

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Hsinchu, Taiwan

Yen-Tso Chen