Realtek Semiconductor Inc.

Yen-Ting Wu

Shih-hsiung Huang

Jun Yang

Wei-cian Hong

The present invention discloses a switched capacitor amplifying apparatus having gain adjustment mechanism. An amplifier includes an input terminal and an output terminal. A capacitor circuit includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor array. The sampling capacitor circuit includes two sampling input terminals and a sampling output terminal to receive an input signal from a signal input terminal and output a sampled result to the input terminal of the amplifier. The load capacitor and the level-shifting capacitor array are charged according to the output terminal of the amplifier and the load capacitor is subsequently charged by the level-shifting capacitor array to accomplish level-shifting such that the load capacitor generates an output signal through a signal output terminal. A control circuit determines an enabling combination of level-shifting capacitors included in the level-shifting capacitor array to determine an equivalent capacitance, to further determine a loop gain.

Switched capacitor amplifying apparatus and method having gain adjustment mechanism

A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.

Front-end sampling circuit and method for sampling signal

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.

Bootstrapped switch

A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.

Successive approximation register analog to digital converter device and signal conversion method

The present invention discloses a comparator circuit having false-alarm preventing mechanism. An input pair circuit receives a first and a second input voltages from a first and a second input terminals in an the operation state. The input pair circuit and a latch circuit cooperate to perform comparison thereon in the operation state to generate a first and a second output voltages at a first and a second output terminals. A gate and a drain of a first latch transistor are electrically coupled to the first and the second output terminals respectively. A gate and a drain of a second latch transistor are electrically coupled to the second and the first output terminals respectively. A conduction adjusting circuit enhances the conduction of the latch circuit when being triggered. A voltage detection circuit triggers the conduction adjusting circuit when the first and the second output voltages are not within a predetermined range.

Comparator circuit having false-alarm preventing mechanism and operation method of the same

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

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Hsinchu, Taiwan

Yen-Ting Wu