Taiwan Semiconductor Manufacturing Comp. Ltd.

Cyntec Company

Industrial Technology Research Institute

Tokyo Electron Limited

Realtek Semiconductor Inc.

Yen-Ting Lin

Mahmut Sinangil

Yen-Huei Chen

Hung-Jen Liao

Jonathan Tsung-Yung Chang

Kuo-Shu Kao

Tai-Jyun Yu

Tao-Chih Chang

Wen-Chih Chen

Wei-Kuo Han

Po-Kai Chiu

Ta-Wen Lo

Carlos H Diaz

Yih Wang

Wen-Hsiung Liao

Akitoshi Harada

Kerem Akarvardar

Shigeru Yoneda

Qing Dong

Wu-Liang Chu

Chih-Hsuan Chen

Ju-Chia Hsieh

Hsing-Kai Cheng

Ching-Feng Chen

Shih-Chieh Chen

Sheng-Tsai Wu

Chung-Hsiung Wang

Hideo Ikuta

Yuan-Yin Lo

Yu-Jen Lin

Hsin-Han Lin

Kun-Hong Shih

Wen-hau Yang

Han-Lin Wu

Hung-Hsuan Cheng

Dar-Win Lo

Sung-Chan Yen

Yin-Tien Yeh

Chih Sheng Kuo

Chun-yu Luo

A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.

Single-inductor multi-output (SIMO) direct current to direct current (DC-DC) buck converter

A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Low voltage memory device

A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 &#x3bc;m and 300 &#x3bc;m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

Chip package

Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Series of parallel sensing operations for multi-level cells

Power module

A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

Low voltage bit-cell

A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S).

Plasma processing method and plasma processing apparatus

A resistor device includes a resistor plate having opposite first and second surfaces; a first metal layer including first and second portions which are disposed on the first surface of the resistor plate at opposite first and second sides, respectively; and a second metal layer including a first sensing pad, a second sensing pad, a first current pad and a second current pad, separate from one another, wherein the first sensing pad and the first current pad are disposed on the first portion of the first metal layer and the second sensing pad and the second current pad are disposed on the second portion of the first metal layer. A protective layer is preferably provided, overlying the resistor plate and the first metal layer uncovered by the second metal layer.

Current sensing resistor

Growing community of inventors

Hsinchu, Taiwan

Yen-Ting Lin