Via Technologies, Inc.

Yen-Ting Lai

Wen-Yu Tseng

Hao-Hsuan Chiu

A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.

Control chip and control system utilizing the same

A data link transmitter in a PCI Express device for managing PCI-Express TLPs and DLLPs. The data link transmitter includes a priority system in which a DLLP for initializing flow control has highest priority, and an idle data character has lowest priority. Various embodiments include: a DLLP for power state entrance is lower priority than the DLLP for initializing flow control; a replay TLP for retry buffer re-transmission is lower priority than the DLLP for power state entrance, and a new TLP is lower priority than the replay TLP; an Ack/Nak DLLP is lower priority than the new TLP, a DLLP for updating flow control is lower priority than the Ack/Nak TLP, and a DLLP for acknowledging the DLLP for power state entrance is lower priority than the DLLP for updating flow control; a DLLP for updating flow control is lower priority than the DLLP for power state entrance.

PCI-express data link transmitter employing a plurality of dynamically selectable data transmission priority rules

A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.

Growing community of inventors

Taipei, Taiwan

Yen-Ting Lai