Taiwan Semiconductor Manufacturing Comp. Ltd.

Yen-Ting Chiang

Dun-Nian Yaung

Shyh-Fann Ting

Chun-Yuan Chen

Ching-Chun Wang

Jen-Cheng Liu

Hsiao-Hui Tseng

Wei Chuang Wu

Jhy-Jyi Sze

Yu-Jen Wang

Feng-Chi Hung

Sheng-Chan Li

Min-Ying Tsai

Cheng-Hsien Chou

Tzu-Jui Wang

Yeur-Luen Tu

Yuichiro Yamashita

Shih Pei Chou

Shen-Hui Hong

Yu-Hung Cheng

Chih-Yu Lai

Cheng-Yuan Tsai

Yen-Yu Chen

Keng-Yu Chou

Ming-Hsien Yang

Yimin Huang

Chih-Hui Huang

Tzu-Hsiang Chen

I-Nan Chen

Wei-Chuang Wu

Chia Ching Liao

Kuan-Tsun Chen

Tzu-Hsuan Hsu

Ming-Tsong Wang

Yu-Hsien Li

Wen Hao Chang

Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The substrate comprises a front-side surface opposite a back-side surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the back-side surface toward the front-side surface. The inner isolation structure comprises a second height less than the first height.

Isolation structure to increase image sensor performance

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

Bond pad structure with high via density

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Extra doped region for back-side deep trench isolation

A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Semiconductor structure

Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Composite BSI structure and method of manufacturing the same

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Deep trench isolations and methods of forming the same

The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a boundary deep trench isolation (BDTI) structure disposed at boundary regions of a pixel region surrounding a photodiode. The BDTI structure has a ring shape from a top view and two columns surrounding the photodiode with the first depth from a cross-sectional view. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel region overlying the photodiode, the MDTI structure extending from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure has three columns with the second depth between the two columns of the BDTI structure from the cross-sectional view. The MDTI structure is a continuous integral unit having a ring shape.

Multiple deep trench isolation (MDTI) structure for CMOS image sensor

In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Vertical gate field effect transistor

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.

The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

Metal reflector grounding for noise reduction in light detector

In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

Image sensor having improved full well capacity and related method of formation

The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.

A semiconductor image sensor device includes a semiconductor substrate, a radiation-sensing region, and a first isolation structure. The radiation-sensing region is in the semiconductor substrate. The first isolation structure is in the semiconductor substrate and adjacent to the radiation-sensing region. The first isolation structure includes a bottom isolation portion in the semiconductor substrate, an upper isolation portion in the semiconductor substrate, and a diffusion barrier layer surrounding a sidewall of the upper isolation portion.

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Tainan, Taiwan

Yen-Ting Chiang