Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Yen-Teng Ho

Chenming Hu

Shu-Jui Chang

Kai-Yu Peng

Yi Chang

Chen-Han Chou

Cheng-Hung Shen

Chia-Hsing Wu

Li Yuan Chang

Chen Han Chou

Cheng Hung Shen

Chia Hsing Wu

A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.

Transistors having two-dimensional semiconductor channels

A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

Three dimensional integrated circuit and fabrication thereof

An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

A semiconductor structure includes a substrate, a buffer layer, and a two-dimensional layered material. The buffer layer is above the substrate and is formed from one of SiC and a nitride-based material. The two-dimensional layered material is above the buffer material. The construction as such permits formation, e.g., of a channel of a transistor from the two-dimensional layered material.

Semiconductor structure with template for transition metal dichalcogenides channel material growth

Disclosed is a semiconductor structure comprising a single crystal substrate, a channel layer formed above the substrate from a transition metal dichalcogenides (TMDC) material, and a single crystal epitaxial buffer layer formed between the substrate and the channel layer, wherein the buffer layer is formed from material having a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material. Also, disclosed is a method of forming a semiconductor structure comprising selecting a substrate formed from a single crystal material, preparing the substrate for template growth, growing a template on the substrate wherein the template is formed from single crystal material, and growing channel material on the template wherein the channel material is formed from a TMDC material and wherein the buffer layer material has a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material.

The present invention relates to a method for growing a novel non-polar (130) plane epitaxy layer of wurtzite structure, which comprises the following steps: providing a single crystal oxide with perovskite structure; using a plane of the single crystal oxide as a substrate; and forming a non-polar (130) plane epitaxy layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process. The present invention also provides an epitaxy layer having non-polar (130) plane obtained according to the aforementioned method.

Growing community of inventors

Tainan, Taiwan

Yen-Teng Ho