International Business Machines Corporation

Yen S Yee

Lewis M Terman

Richard B Merrill

Lawrence G Heller

A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Sequential successive approximation analog-to-digital converter

A digital-to-analog conversion (DAC) circuit and trigger comparator combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate in the CCD. The trigger comparator adjacent to a second gate in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state. In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator switches state, the digital input to the DAC at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure is employed as the multi-level CCD memory system.

Multi-level charge-coupled device memory system including

A functional and structural arrangement for charge-coupled device binary or multi-level storage systems of a modified serial-parallel serial type memory block arrangement wherein the output sequence is removed from the memory block proximate to the location where the original sequence was entered into the memory block. The structure includes two memory block portions designated as the left and right memory block portions. The input information sequence is entered into the upper left side of the right memory block portion in serial fashion, is moved in parallel to the bottom of the right memory block portion and serially removed from the lower left side of the right memory block portion and entered into the lower right side of the left memory block portion. The sequence is moved in parallel to the top of the left memory block portion and serially removed from the upper right side of the left memory block portion proximate to the original input location for comparison to the reference charge sequence in an analog-to-digital regeneration operation utilizing the same digital-to-analog converter.

Loop organized serial-parallel-serial memory storage system

A two-stage weighted capacitor network for use as an analog-to-digital or digital-to-analog converter is described. A capacitor ladder is included having two similar groups of capacitors connected in parallel. In each group the parallel capacitors have values starting with value C and decreasing in binary fractional amounts C/2.sup.1, C/2.sup.2, C/2.sup.3, C/2.sup.4 etc. to C/2.sup.n-1. The two groups are interconnected through a coupling capacitor of value C/2.sup.n-1 and each of the capacitors in the two groups are selectively connected through switches to either a reference voltage or ground potential. A high gain amplifier connected as an inverting amplifier with a 2C capacitor feedback path is connected to the capacitor ladder. When the circuit is used in a digital-to-analog converter, the 2C capacitor is reset and then the digital input pattern, consisting of 2n bits, is manifested by connecting the capacitor ladder switches to the ground potential for '1' bits and leaving the other switches connected to the reference potential for '0' bits. When the circuit is used in an analog-to-digital converter the output of the amplifier is connected to a comparator which serves as a polarity detector and which feeds a set of control logic. The control logic then sets the switches, which were originally all connected to the analog voltage, in a binary search mode.

Two-stage weighted capacitor circuit for analog-to-digital and

The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.

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White Plains, NY, United States of America

Yen S Yee