Novatek Microelectronics Corp.

Yen-Po Chen

Chao-Chih Hsiao

Tse-Hung Wu

Ching-Ho Hung

Bor-Chun Wu

A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage.

Gate driving circuit and related LCD device capable of separating time for each channel to turn on thin film transistor

A gate driving circuit and a driving method thereof are provided. The gate driving circuit includes a control signal generator and at least one gate channel set, each of the at least one gate channel set includes a plurality of gate channels, and the plurality of gate channels share a level shifter. The driving method includes generating a plurality of first control signals and a plurality of second control signals according to a gate driver start pulse, and determining that one of the gate channels uses the level shifter during a time period according to the plurality of first control signals and the plurality of second control signals. Therefore, the number of the level shifters can be decreased.

Gate driving circuit and driving method thereof

A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced.

Shift register apparatus

A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.

Growing community of inventors

Hsinchu, Taiwan

Yen-Po Chen