Industrial Technology Research Institute

Yen-Pin Tseng

Chau-Chin Su

Kuan-Ming Lin

Hung-Wen Lu

Ja-Nan Wang

Hsueh-Chin Lin

Tzu-Jian Yang

Jeffrey Liu

Chien-Hsi Lee

Chia-Nan Wang

Uan-Jiun Liu

A system for clock and data recovery ('CDR') includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.

High-speed serial link clock and data recovery

An Ethernet passive optical network (EPON) ring for providing protection against fiber failures. The optical network unit (ONU) is coupled to the ring fiber by a three-port passive optical splitting module that has three two-way optical passages. By the three two-way optical passages, the OUN receives/transmits data from/to the two ends of the optical line termination (OLT) to provide protection while the fiber failure. Moreover, it provides better authorization of users and simpler collision detection by the two-way transmission of the three-port passive optical splitting module to prevent hackers from invading and to reduce collisions.

Ethernet passive optical network ring and its method of authorization and collision detection

Growing community of inventors

Hsinchu, Taiwan

Yen-Pin Tseng