Taiwan Semiconductor Manufacturing Comp. Ltd.

Yen-Ling Liu

Nan-Hsin Tseng

Ji-Jan Chen

Bo-Jr Huang

Samuel C Pan

Wei-Pin Changchien

Kuen-Jong Lee

Cheng-Hung Wu

Hui-Ling Lin

Wei-Cheng Lien

A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.

Defect diagnosis

A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within a beam. The method further includes converting, with a number of diodes connected to a positive voltage supply, an electrical current signal created by the electron beam to a voltage signal, wherein the number of diodes includes a diode stack of multiple diodes. The method further includes extracting, with a digital inverter, a test signal from the voltage signal.

Contactless signal testing

A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within an electron beam, converting an electrical current created by the e-beam to a voltage with a number of diodes connected to a positive voltage supply, extracting a digital test signal from the voltage signal with a digital inverter, and passing the test signal to digital circuitry within the integrated circuit.

The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

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Hsinchu, Taiwan

Yen-Ling Liu