Realtek Semiconductor Inc.

Mediatek Corporation

Yen-Ju Lu

Wen-Chou Wu

Chih-Ming Hung

Nan-Cheng Chen

Shih-Chia Chiu

Che-Ya Chou

Chao-Wei Huang

Wen-Sung Hsu

Tao Cheng

Wei-Hsiu Hsu

Yi-Chieh Lin

Sheng-Mou Lin

Ying-Chou Shih

Jui-Yuan Lin

Ching-Yeh Yu

Yu-Ming Chang

Debapratim Dhara

Hsing-Chih Liu

Chang-Lin Wei

Jui-Lin Hsu

Po-Sen Tseng

Yeh-Chun Kao

Ying-Chih Chen

Chen-Tung Lin

ChiaYu Lin

Sheng-Wei Lei

Jiunn-Nan Hwang

Chih-Yang Liu

Yu Chun Lu

Sheng-Yuan Jan

Chia-Yu Lin

Yu-Chun Lu

An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.

High gain and fan beam antenna structures

A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

Antenna-in-package with frequency-selective surface structure

A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Semiconductor package with layer structures, antenna layer and electronic component

A radar module includes a printed circuit board (PCB) and a semiconductor package mounted on the PCB. The semiconductor package comprises an integrated circuit die and a substrate for electrically connecting the integrated circuit die to the PCB. The substrate comprises an antenna layer integrated into the semiconductor package and electrically connected to the integrated circuit die for at least one of transmitting and receiving radar signals. A discrete pattern-shaping device is mounted on the PCB and is configured to shape a radiation pattern of the radar signals.

Radar module incorporated with a pattern-shaping device

High gain and fan beam antenna structures and associated antenna-in-package

The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

Memory data access apparatus and method thereof

A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.

Test kit for testing a device under test

A circuit system includes a first circuit, a second circuit, and a comparator. The second circuit and the first circuit have substantially identical structures. In a testing mode, the circuit system controls the first circuit and the second circuit to perform the same testing operation synchronously. During the process of the testing operation, the comparator keeps compares a first intermediate signal internally generated by the first circuit and a second intermediate signal corresponding to the first intermediate signal that is internally generated by the second circuit. When the first intermediate signal is different from the second intermediate signal, the circuit system controls the first circuit and the second circuit to stop the testing operation and controls the first circuit and the second circuit to perform a scan dump operation in order to record signals transmitting by the first circuit and signals transmitting by the second circuit.

Method for testing a circuit system and a circuit system thereof

A data write system includes a processor circuit, a first memory, at least one register, and a second memory. The first memory is coupled to the processor circuit. The at least one register is configured to define at least one range. The second memory is coupled to the first memory. If a cache miss occurs and an access address of a reading command is in the at least one range in the second memory, a predetermined amount of data corresponding to the access address is written from the second memory into at least one first way of the first memory.

Data write system and method with registers defining address range

A linked list searching method and device are configured to search a linked list by using a cache memory. The method includes the operations of: writing the linked list in a memory; writing the data of a first node in a first row of a tag memory of the cache memory, and writing an address of the first node in a first row of a data memory of the cache memory; writing the data of a second node in a second row of the tag memory, and writing the address of the second node in a second row of the data memory; and searching the data of the second node in the tag memory to directly retrieve the address of the second node when searching the address of the second node in the linked list according to the data of the second node.

Linked list searching method and linked list searching device

A processor circuit is provided. The processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a load instruction to generate a decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instruction is in a load-use scenario. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the load instruction according to the decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instruction is in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.

Processor circuit and data processing method

A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

A semiconductor package includes a substrate, an electronic component, a dielectric layer a transmitting antenna, a receiving antenna and a FSS (Frequency selective surface) antenna. The electronic component is disposed on and electrically connected with the substrate. The dielectric layer has a dielectric upper surface. The transmitting antenna and the receiving antenna are formed adjacent to the substrate. The FSS antenna is formed adjacent to the dielectric upper surface of the dielectric layer. The FSS antenna is separated from the substrate by the dielectric layer in a wireless signal emitting direction.

Semiconductor package

A cache and a method for managing a cache are provided. The cache includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit stores data in a first-in first-out (FIFO) manner. The control circuit is coupled to the storage circuit and the buffer circuit and is configured to find a storage space in the storage circuit and write the data to the storage space.

Growing community of inventors

Hsinchu, Taiwan

Yen-Ju Lu