Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Yen-Ju Chen

Hui-Chi Chen

Chia-Wei Chen

Kuo-Feng Yu

Jian-Hao Chen

Wei-Cheng Wang

Shih-Hang Chiu

Wei Cheng Hsu

Kuang-Chao Chen

Shih-Ping Hong

Chun-Chih Cheng

Yuan-Chieh Chiu

Kuan-Ting Liu

Wei-Cheng Hsu

Yung-Hsiang Chan

Chih-Ming Sun

Jo-Chun Hung

Wei-Chen Hsiao

Yen-Ta Lin

Yun-chen Wu

Wen-Yao Yang

Te-Fu Yeh

A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.

Semiconductor device structure and method for forming the semiconductor device structure

A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Forming low-resistance capping layer over metal gate electrode

A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Metal gate cap

Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Method of fabricating semiconductor device

Semiconductor device and method of fabricating the same

Growing community of inventors

Hsinchu, Taiwan

Yen-Ju Chen