Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Tsinghua University

Yen-Huei Chen

Hung-Jen Liao

Hidehiro Fujiwara

Chih-Yu Lin

Jonathan Tsung-Yung Chang

Wei Min Chan

Wei-Cheng Wu

Hsien-Yu Pan

Kao-Cheng Lin

Li-Wen Wang

Sahil Preet Singh

Shao-Yu Chou

Jung-Hsuan Chen

Jhon Jhy Liaw

Chiting Cheng

Chien-Chen Lin

Mahmut Sinangil

Yi-Hsin Nien

Cheng Hung Lee

Yu-Hao Hsu

Wei-Chang Zhao

Wei-Min Chan

Haruki Mori

Tzu-Kuei Lin

Ping-Wei Wang

Yangsyu Lin

Yih Wang

Chia-En Huang

Jui-Jen Wu

Jhon-Jhy Liaw

Chen-Lin Yang

Jung-Ping Yang

Cheng-Hung Lee

Yen-Ting Lin

Pankaj Aggarwal

Chien-Kuo Su

Chi-Ting Cheng

Avinash Chander

Li-Chun Tien

Yasutoshi Okuno

Shih-Chi Fu

Min-Chang Liang

Fang Chen

Ren-Fen Tsui

Albert Ying

Shih-Lien Linus Lu

Fu-An Wu

Chun-Jiun Dai

Jihi-Yu Lin

Lee-Chung Lu

Hong-Chen Cheng

Jui-Che Tsai

You-Cheng Xiao

Chien-Chi Tien

Zhi-Hao Chang

Pei-Yuan Li

Manish Arora

Nikhil Puri

Chien Chi Linus Tien

Feng-Lun Chen

Chih-Cheng Yu

Jiun Yi Wu

Meng-Sheng Chang

Yun-Han Lee

Hiroki Noguchi

Kuo-Ching Hsu

Kai-Ming Ching

Yung-Lung Lin

Tze-Chiang Huang

Huai-Ying Huang

Shih-Cheng Chang

Dao-Ping Wang

Geng-Cing Lin

Ze-Sian Lu

Jin-Lien Lin

Ping Wang

Yen Lin Chung

Yu-Der Chih

Meng-Fan Chang

Yi-Chun Shih

Chia-Fu Lee

Ching-Wei Wu

Hau-Tai Shieh

Yi-Tzu Chen

Po-Hao Lee

Kun-Lung Chen

Tetsu Ohtou

Ming-Yi Lee

Ru-Yu Wang

Hsin-Hsin Ko

Chien Chi Tien

Gary Chan

Hsiu-Hui Yang

Zhi-hao Chang

Mohammed Hasan Taufique

Fang Jao

A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.

4CPP SRAM cell and array

A memory macro includes an input/output (I/O) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the I/O circuit in the semiconductor wafer, wherein the first subset is positioned between the I/O circuit and the second subset, a first bit line coupled to the I/O circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the I/O circuit and extending on the other of the frontside or the backside along the first and second subsets. Each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.

Memory device, method, layout, and system

A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including local write drivers correspondingly coupled to the segments; and a global write driver coupled to each of the local write drivers.

Semiconductor device including distributed write driving arrangement

A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

Memory array circuit and method of manufacturing same

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Multi-stage bit line pre-charge

Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.

Memory device including separate negative bit line

A method of performing an in-memory computation includes storing a first subset of data in a first segment of a first memory array and a second subset of the data in a second segment of the first memory array, latching a first data bit from a first column of memory cells in the first segment of the first memory array, sequentially reading a plurality of second data bits from a second column of memory cells in the second segment of the first memory array, and performing a logic operation on each combination of the latched first data bit and each second data bit.

Memory computation method

A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

Memory device having a negative voltage circuit

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Voltage regulator with power rail tracking

An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line; and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's. The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.

Bitcell supporting bit-write-mask function

A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.

Integrated circuit, system and method of forming the same

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Integrated circuit die with memory macro including through-silicon via and method of forming the same

A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Memory device with additional write bit lines

A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.

Memory devices with improved bit line loading

A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.

Static random access memory with a supplementary driver circuit and method of controlling the same

Growing community of inventors

Jhudong, Taiwan

Yen-Huei Chen