Taiwan Semiconductor Manufacturing Comp. Ltd.

Yen-Hao Huang

Sandeep Kumar Goel

Yun-Han Lee

Ji-Jan Chen

Stanley John

Shy-Jay Lin

Hsin-Cheng Chen

Jung-Rung Jiang

Jensen Yang

I-Shi Wang

Sheng-Yuan Lin

Chun-Yi Chen

Yuan-Hsin Chi

Yin-Tun Chou

A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.

Semiconductor substrate bonding tool and methods of operation

Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Active random access memory

A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

Phase-locked loop monitor circuit

A method for routing data for an e-beam writer includes, with a switching device of the e-beam writer, receiving a packet. The method further includes, with a scheduling engine of the switching device, routing the packet to one of a plurality of output buffers, wherein the routing is based on availabilities of the plurality of output buffers and vacancy levels of memory devices associated with the plurality of output buffers. The method further includes, with the switching device, outputting the packet from an output port associated with a memory device to which the packet is routed.

Data processing of electron beam lithography system

A method includes receiving, by an input buffer of a switching device, a packet, determining, by a scheduling engine of the switching device, a destination output buffer for the packet, receiving, by the scheduling engine of the switching device, an availability of the destination output buffer and a vacancy level of a memory device that is associated with the destination output buffer, and based on the availability of the destination output buffer and the vacancy level of the memory device, determining, by the scheduling engine of the switching device, a routing destination of the packet. The routing destination includes the input buffer, the destination output buffer, and the memory device.

A system includes a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable; a switching device that is coupled to the DPG, the switching device configured to route a packet to the DPG so as to control at least one of the pixels, the switching device further comprising: a plurality of input buffers configured to receive and store the packet through a transmission line; a plurality of output buffers; a plurality of memory devices, wherein each of the plurality of memory devices is associated with one of the plurality of output buffers; and a scheduling engine that is coupled to the plurality of input buffers, the plurality of output buffers, and the plurality of memory devices and is configured to determine a routing path for the packet stored in one of the input buffers based on an availability of the output buffers and a vacancy level the memory devices.

Growing community of inventors

Hsin-Chu, Taiwan

Yen-Hao Huang