Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Yen-Chung Tony Chen

Tsai-Ming Yang

Wen-Juh Kang

Ting-Hsu Chien

Chen-Yang Pan

Igor Elkanovich

Amnon Parnass

Yi-Lin Lee

Chia-Hsiang Chang

Ting-Hao Wang

Pei Yu

Jia-Liang Chen

Yuan-Hung Lin

Jen-Tai Hsu

Chung-Kai Wang

Li-Hua Lin

Yu-Ju Chang

Ting-Chin Cho

Wen-Lung Tu

Chao-Ching Huang

Li-Ya Tseng

Yen-Wei Chen

Zanyu Yang

Wei-An Liang

Chun-Hsu Chen

An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180&#xb0; with respect to a row direction and a column direction.

Interface of integrated circuit die and method for arranging interface thereof

A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.

Circuit of communication interface between two dies and method to manage communication interface

A voltage mode signal transceiving device and a voltage mode signal transmitter thereof are provided. The voltage mode signal transmitter includes a driver, an output resistor, and a compensation capacitor. The driver provides a transmitting signal to an output end, where the output end is coupled to a receiver. The output resistor is connected in series to a coupling path between the driver and the receiver. The compensation capacitor and the output resistor are coupled in parallel. A capacitance value of the compensation capacitor is essentially equal to a capacitance value of an equivalent capacitor on an input end of the receiver.

Voltage mode signal transceiving device and voltage mode signal transmitter thereof

A clock and data recovery (CDR) circuit is provided, and includes a sampling circuit, an error sampler, a phase detect circuit, and a phase adjust circuit. The sampling circuit generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect circuit receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect circuit stops transmitting the corrective signal. The phase adjust circuit generates and adjusts the first and the second clock signal according to the corrective signal.

Clock and data recovery circuit and method

A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Device and method for recovering clock and data

A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Current-mode logic latch circuit

A clock data recovery system is provided. A CTLE generates a first equalized signal. An adder superposes the first equalized signal and a feedback equalization signal and generates a superposed signal. A first error slicer slices the superposed signal according to a clock signal and a reference voltage and generates a first error signal. A second error slicer slices the superposed signal according to the clock signal and a second slicing voltage. A data slicer slices the superposed signal according to the clock signal and a third slicing voltage and generates a data signal. A CDR circuit generates the clock signal. An adaptive filter receives the data signal and the first error signal, and generates the reference voltage and a DFE coefficient set. A DFE receives the data signal and the DFE coefficient set, and generates the feedback equalization signal.

Clock data recovery system for Serdes

An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.

Active inductor and associated amplifying circuit

An oscillation circuit and associated method, wherein the oscillation circuit provides a pair of oscillation signals at two oscillation nodes, and includes a first capacitor, a switch circuit and a second capacitor serially coupled between the two oscillation nodes; the switch circuit conducts between the first capacitor and the second capacitor on an enable voltage higher than a power voltage of the oscillation circuit.

Oscillation circuit and associated method

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Santa Clara, CA, United States of America

Yen-Chung Tony Chen