Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Realtek Semiconductor Inc.

Raymx Microelectronics Corp.

Sun Microsystems, Inc.

Lite-on Technology Corporation

Scintera Networks, Inc.

Yen-Chung Chen

Chih-Ching Chien

Tsai-Ming Yang

Wei-Ren Hsu

Cheng-Yu Chen

Wen-Juh Kang

Ting-Hsu Chien

Yi-Lin Lee

Liang-Hung Chen

Ming-Yuh Yeh

Cheng-Hung Wu

Yi-Ting Wei

Li-Chun Huang

Jiunn-Jong Pan

Fu-Hsin Chen

Yi-Jen Chen

Chih-Yen Chen

Hamid Reza Rategh

Chia-Hsiang Chang

Po-Shing Yu

Wang-Sheng Lin

Ju-Chieh Wang

Jen-Tai Hsu

Jung-Chi Huang

Sung-Hun Oh

Wen-Lung Tu

Kailashnath Nagarakanti

Yufeng Zhou

Chi-Sian Chuang

Tzu-Yu Chao

Shan-Jie Wang

Cho-Ru Yang

Han-Ting Tsai

Wen-Hsin Chang

Yun-Tzuo Lai

A NAND flash memory controller can adjust its processing power according to a host speed and thereby save energy. The controller includes: a host speed estimation module estimating the host speed according to a first total data amount of the host's M first I/O command(s) received by the controller within a first period of time, the host speed correlating with the host's demand for access; a controller speed estimation module estimating a controller speed according to a second total data amount of the host's N second I/O command(s) completed by the controller within a second period of time, the controller speed correlating with the processing power of the controller; a speed decision module generating a decision result according to the relation between the host speed and the controller speed; and a speed adjustment module adjusting or maintaining the processing power of the controller according to the decision result.

NAND flash memory controller capable of adjusting its processing power according to its speed

A solid-state drive (SSD) controller is operable to determine whether M supply voltage(s) supplied to a NAND flash memory is correct. The SSD controller includes: a voltage detector configured to receive the M supply voltage(s) and thereby generate a detection result, wherein the M is a positive integer; a voltage inquiry module configured to output an inquiry signal to the NAND flash memory and thereby receive a response signal from the NAND flash memory, and configured to generate an inquiry result according to the response signal, wherein the inquiry result indicates M specified supply voltage(s) applicable to the NAND flash memory; and a voltage decision module configured to receive the detection result and the inquiry result, and configured to determine whether the M supply voltage(s) is/are equivalent to the M specified voltage(s) according to the detection result and the inquiry result and thereby generate a decision result.

Solid-state drive controller and circuit controller

A storage device includes a controller and a memory. A method of storage space management for the storage device is executed to perform steps as below. The controller calculates an expectedly used capacity and an effective capacity of the memory. The controller determines whether blocks of the memory include one or more blocks that are non-bad blocks and are prohibited from reading/writing. When the one or more blocks are determined to be non-bad blocks and to be prohibited from reading/writing, the controller marks each of the one or more blocks as a restricted block other than a bad block, thereby maintaining the effective capacity to be unchanged. The controller compares difference of the effective capacity and a total capacity of the one or more blocks that are marked as the restricted block to the expectedly used capacity to determine whether to prohibit programming to the memory.

Method of storage space management for improving endurance of storage devices

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

Data processing method and memory controller utilizing the same

A data processing method includes: configuring a predetermined memory space to record information regarding data to be backed up of a memory device, where the information is used to indicate data associated to which logical memory space is the data to be backed up; and updating the information according to commands received from a host device.

A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.

Testing device and testing method

A clock data recovery device includes a phase detector circuitry, a signal control circuitry, and interpolators. The phase detector is configured to detect a phase of an input signal, according to first clock signals, to generate first control signals, and phases of the first clock signals are different to each other. The signal control circuitry is configured to rearrange the first control signals to output as second control signals. The phase interpolators are configured to output second clock signals and alternatively adjust the phases of the second clock signals according to the second control signals to generate an output clock signal.

Clock data recovery device and method to alternatively adjust phases of outputted clock signals

An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.

Amplifier device and offset cancellation method

The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Memory controller and method having predictive buffering of address mapping table

A multi-channel transmission device is provided. The multi-channel transmission device includes a clock generator and a plurality of transmitters. The clock generator generates input clocks. The transmitters operate based on spread spectrum clocks respectively. Each of the transmitters comprises a phase rotator. The phase rotator provides a selection signal and an interpolation signal of multiple bits. The phase rotator selects two of the input clocks as a first selected input clock and a second selected input clock according to the selection signal, and generate a spread spectrum clock according to the interpolation signal, the first selected input clock and the second selected input clock.

Multi-channel transmission device

A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.

Memory device for guaranteeing a mapping table and method thereof

A voltage mode signal transmitter includes a front-end signal processor and a signal transformer. The front-end signal processor receives a first and second data signal, and delays and inverts the data signals to generate a third and fourth data signal. The front-end signal processor selects two of the first data signal to the fourth data signal to generate a plurality of signal pairs according to a first control signal. The signal transformer selects one data signal of each of the signal pairs to generate input voltages according to a second control signal, and generates an output voltage according to the input voltages. A working frequency of the first control signal is lower than a working frequency of the second control signal.

Voltage mode signal transmitter

An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.

Data storage device and operation method of the same

A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.

System and method for accessing a storage device

The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is important data or unimportant data to generate a determination result. The microprocessor is configured to write the data into a flash memory module according to the determination result, wherein the flash memory module comprises a plurality of first blocks and a plurality of second blocks, and quantity of bits stored in each memory cell within the first blocks is lower than quantity of bits stored in each memory cell within the second blocks. When the determination result indicates that the data is the important data, the microprocessor only stores the data into at least one of the first blocks.

Growing community of inventors

Hsinchu, Taiwan

Yen-Chung Chen