Taiwan Semiconductor Manufacturing Comp. Ltd.

Philips & Lite-on Digital Solutions Corporation

Yen-Chun Lin

Da-Wen Lin

Ming-Lung Cheng

Hung-Wen Su

Chia-Ling Chan

Shu-Cheng Chin

Ming-Yuan Gao

Bao-Ru Young

King-Yuen Wong

Chih-Chien Chi

Chien-Chang Su

Pei-Hsuan Lee

Yi-Fang Pai

Chih-Hsiang Chang

Yen-Sen Wang

Chi-Feng Lin

Chia-Yu Lu

Hsin-Ying Peng

Chen-Yi Niu

Chun-Chieh Lin

Chung-Cheng Wu

Chung-Yi Lin

Kai-Shiang Kuo

Cheng-Hui Weng

Yao-Min Liu

Huei-Wen Hsieh

Tun-Chieh Lee

Ting-Yun Wu

Che-Min Chu

Chih-Hung Tseng

Tsung-Hung Li

Ming-Chou Chiang

Tsung-Yu Lu

Hung-Lung Tseng

Hsiao-Wen Hsu

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Method of forming interconnect structure having a barrier layer

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Ruthenium-based liner for a copper interconnect

A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

FinFET device with different liners for PFET and NFET and method of fabricating thereof

Interconnect structure and method of forming thereof

Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

Test line structure, semiconductor structure and method for forming test line structure

A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

Semiconductor device

A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

FinFET device and method of forming same

A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping.

Semiconductor device and method

Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

Method and apparatus of forming an integrated circuit with a strained channel region

A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.

Device with engineered epitaxial region and methods of making same

An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Method for enhancing channel strain

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Hsinchu, Taiwan

Yen-Chun Lin