Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Tsinghua University

Mobiletron Electronics Co., Ltd.

Mediatek Corporation

Ledlas Corp.

Yen-Chieh Huang

Chung-Te Lin

Hai-Ching Chen

Sai-Hooi Yeong

Yu-Ming Lin

Chia-Ta Yu

Po-Ting Lin

Feng-Cheng Yang

Song-Fu Liao

Yen-Ming Chen

Wei-Yuan Lu

Yean-Jenq Huang

Shu-Hua Chang

Han-Ting Tsai

I-Hsieh Wong

Tsann Lin

Ching-Huang Wang

Cheng-I Teng

Yen-Yin Lin

Min-Kun Dai

An-Chung Chiang

Tsung-Yi Yu

Ming-Hsiung Wu

Yi-Hsien Tu

Kuoyuan (Peter) Hsu

Chih-Yu Chang

Kai-Hsuan Lee

Ken-Ichi Goto

Kuo-Chang Chiang

Sung-Chieh Lin

Chia-Hsiang Chen

Po-Hung Chen

Min-Hao Chiu

Ya-Ling Lee

Wei-Gang Chiu

Chin-Huang Wang

Jow-Tsong Shy

Yi-Chu Wang

Yen-Hung Chen

Shou-Tai Lin

Tsong-Dong Wang

Kuan-Yan Huang

Guey-Wu Chang

Yueh-Lin Wu

Yu-Chung Chiu

Po-Cheng Wang

A single-material-double-process parametric laser-wavelength converter includes a pump-laser source, a nonlinear optical material, a first optical reflective element, and a second optical reflective element. The pump-laser source is configured to emit a pump-laser pulse light. The nonlinear optical material receives the pump-laser pulse and generates a signal-laser pulse and a partially depleted pump-laser pulse through optical parametric amplification. The first optical reflective element is configured to reflect the signal-laser pulse back to the same nonlinear optical material. The second optical reflective element is configured to reflect the partially depleted pump-laser pulse back to the same nonlinear optical material. With an appropriate adjustment on the reflecting path lengths, the nonlinear optical material is configured to receive the temporally synchronized signal-laser pulse and the partially depleted pump-laser pulse to generate an idler output through difference frequency generation. Both optical parametric amplification and difference frequency generation occur in the same nonlinear optical material.

Single-material-double-process parametric laser-wavelength converter

The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

Epitaxial layer under a gate structure of a transistor

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Memory device and method for fabricating the same

An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Ferroelectric memory device with a metal layer having a crystal orientation for improving ferroelectric polarization and method for forming the ferroelectric memory device

A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

Semiconductor structure and method of forming the same

Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

Double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure

A thin-film transistor includes a flexible substrate, an amorphous semiconductor channel layer on the flexible substrate, an organic material piezoelectric stress gate layer adjacent to the amorphous semiconductor channel layer, a gate electrode adjacent to the organic material piezoelectric stress gate layer, and a source electrode and drain electrode coupled to the organic material piezoelectric stress gate layer.

Organic gate TFT-type stress sensors and method of making and using the same

A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Semiconductor device with self-aligned wavy contact profile and method of forming the same

A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes outer spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes an inner spacer structure between the first fin and the second fin and covering inner sidewalls of the epitaxial structure. A top surface of the inner spacer structure is exposed to an air gap formed between the epitaxial structure and the inner spacer structure.

Semiconductor structure having epitaxial structure

A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

Semiconductor devices with ferroelectric layer and methods of manufacturing thereof

Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.

Metal layers for increasing polarization of ferroelectric memory device

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Three dimensional metal insulator metal capacitor structure

A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.

Wide-bandgap semiconductor layer characterization

A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.

Method for forming semiconductor structure

A dielectric-grating waveguide free-electron laser device generating coherent or laser-like radiation is provided. An electron beam propagates next to a dielectric waveguide with a built-in grating structure to generate highly confined coherent or laser-like radiation in the waveguide through the Bragg resonance, the backward-wave resonance, or the Fabry-Perot resonance provided by the grating-waveguide structure. The dielectric-grating waveguide can be made of linear optical materials or nonlinear optical materials or combination of linear and nonlinear optical materials to enable versatile functionalities, such as laser generation, laser-wavelength conversion, and laser signal processing. Owing to the build-up of the laser modes inside the dielectric waveguide, coherent or laser-like Smith-Purcell radiation is also generated above the grating via coupling and bunching of the electrons with the surface mode fields.

Dielectric-grating-waveguide free-electron laser

Growing community of inventors

Hsinchu, Taiwan

Yen-Chieh Huang