Juniper Networks, Inc.

Philips Electronics North America Corporation

Cavium Networks, Inc.

Shopkick, Inc.

Yen C Lee

Nazar A Zaidi

Elango Ganesan

Michael Freed

Ramesh Panwar

Mark Bryers

Sankar Ramanoorthi

John Phillips

Gregory G Spurrier

Yuhong Zhou

David T Hass

Robert G Hathaway

Abbas Rashid

Frederick R Gruner

Ricardo Ramirez

Mark Vilas

Chau Anh Ngoc Nguyen

Michael A Ang

Eino Jacobs

Hari Hampapuram

Richard Eugene Kessler

Aaron T Emigh

Gerrit Ary Slavenburg

Steven Stanek

Vijay K Mehra

Yong H Cho

Gregg Alan Bouchard

David Asher

Thomas Frederick Hummel

Pieter Sierd Van Der Meulen

Muhammed R Hussain

Chau Ahn Ngoc Nguyen

Pieter Van Der Muelen

Various presence detection techniques are disclosed. In some embodiments, a system comprises a signal generator configured to generate a signal that includes a plurality of selected frequencies that are selected from among a set of candidate frequencies, wherein inclusion or exclusion of each candidate frequency in the signal encodes a bit of information and wherein the encoded information comprises a store identifier that identifies a retail store; and a transmitter configured to transmit the signal within the retail store; wherein presence of a device in the retail store is determined in response to reception of the signal at the device and extraction of the store identifier from the received signal by decoding the received signal.

Method and system for presence detection

The transmission system transmits an encrypted identifier ultrasonically in an open-air environment using an ultrasonic transmitter. The ultrasonic identifier is associated with a location, which may be a store or a department within a store, and may be received by a microphone on a mobile phone. The identifier may be used to infer presence of the mobile phone user at the location associated with the identifier. The transmitter may include an ultrasonic transducer. The system may further provide a reward, responsive to inferring presence at the location.

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Content service aggregation system

A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.

Packet queuing, scheduling and ordering

A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.

Store instruction ordering for multi-core processor

An architecture for controlling a multiprocessing system to provide at least one network service to subscriber data packets transmitted in the system using a plurality of compute elements, comprising a management compute element including service set-up information for at least one service and at least one processing compute element applying said at least one network service to said data packets and communicating service set-up information with the management compute element in order to perform service specific operations on data packets. In a further embodiment, a method of controlling a processing system including a plurality of processors is disclosed. The method comprises the steps of operating at least one of said processors as a control authority providing service provisioning information for a subscriber; and operating a set of processors as a service specific compute element responsive to the control authority, receiving provisioning information from the subscriber and performing service specific instructions on data packets to provide IP content services.

Content service aggregation device for a data center

Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e., low cost and chip count, and advantages of a general-purpose processor reprogramability. These custom operations work in a computer system which supplies input data having at least two operand data, performs operations on the operand data, and supplies result data to a destination register.

Method and apparatus for custom operations

Method and apparatus for custom operations of a processor

Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Compressed instruction format for use in a VLIW processor and processor

The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and linked object module produced by a compiler and/or linker and code for swizzling the compiled and linked software to produce a second object module. The second object module is suitable for being deswizzled upon reading from a cache memory using a cache structure whose output bus wires are not crossed.

Compiler generating swizzled instructions usable in a simplified cache

Software for producing instructions in a compressed format for a VLIW

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San Jose, CA, United States of America

Yen C Lee