Motorola Corporation

Yehuda Volpert

Yoram Horen

Judah L Adelman

Gabriel Bracha

Nathan Baron

Ilan Algor

Alick Einav

Eytan Weissberger

Alick Einaj

A method for forming one or more redundant vias (38a-38x) around a critical via (36) involves providing an integrated circuit design file (12) containing several overlay layers. Critical vias in the file (12) are identified via a step (16). Several redundant vias are serially placed around and connected in parallel to the critical via (36), and design rules are checked for each redundant via by performing steps (24-30). Redundant vias which do not violate design rules (26) are kept in a separate redundant overlay layer and added to the design of the integrated circuit. The added redundant vias increase the yield of the integrated circuit by bolstering the integrity of critical via connections.

Method and apparatus for forming redundant vias between conductive

A mantissa addition system (2) having a mantissa adder (6) for adding two mantissas provides an addition result a plurality of bits arranged in sub-groups. The mantissa addition system also has a flag generator which generates a flag for each sub-group: each flag having an active state when all the bits in the respective sub-group are zero and an inactive state when at least one of the bits in the respective sub-group is non-zero. A first detector (46) determines the most significant flag that has the inactive state and provides a first control signal representative of the detected most significant flag. A first shifter (40) shifts the groups of bits of the addition result in response to the first control signal so that the sub-group of bits corresponding to the detected most significant flag is the most significant group. A second detector (48) detects the most significant bit of the most significant sub-group of the shifted result that is non-zero and provides a second control signal representative of the detected most significant bit. A second shifter (42) shifts the plurality of bits of the shifted result in response to the second control signal so that the detected most significant non-zero bit is the most significant bit. The output (8) of the second shifter represents the normalised addition result. The shift information (N) is generated by logic means (52, 54) from the first and second control signals.

Mantissa addition system for a floating point adder

An exponent subtractor system (226) for a floating point adder (200) generates an exponent result (EXP.sub.-- low) and a rounded exponent result (EXP.sub.-- high) for an addition operation performed on two floating point numbers and generates overflow (Overflow.sub.-- low, Overflow.sub.-- high) and underflow flags (Underflow.sub.-- low, Underflow.sub.-- high) for the exponent result and the rounded exponent result before the completion of the updating of the exponent result in an exponent subtractor (52, 72).

Detection of exponent underflow and overflow in a floating point adder

A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal. The lock detection circuit further includes a second counter (6) for counting transitions of the reference signal (REFERENCE), and being coupled to the circuit for generating whereby the second counter is reset by the first (UP) or second (DOWN)pulse, the second counter (6) on counting a predetermined number of transitions of the reference signal providing a second count complete signal, and a logic circuit (20) for generating a signal (LOCK) indicating lock has been achieved in response to the receipt of either the first or second count complete signal. Preferably, the lock detection circuit further includes a pulse width detection circuit (30) for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counter.

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Petach Tikva, Israel

Yehuda Volpert