Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Il Ltd.

Macrovision Corporation

Macrovision Europe Limited

Yehuda Hahn

Shay Benisty

Ariel Navon

Alexander Bazarsky

Ramanathan Muthiah

Alon Marcu

Avichay Haim Hodes

Gadi Vishne

Donald Ray Bryant-Rich

Joseph Robert Meza

Eran Sharon

Daniel Joseph Linnen

Daniel Edward Tuers

Hadas Oshinsky

Karin Inbar

Yacov Duzly

Alex Bazarsky

In-Soo Yoon

Idan Alrod

Eran Erez

Dmitry Vaysman

Israel Zimmerman

Michael Micha Ionin

Ran Zamir

Itzhak Pomerantz

Abhijeet Manohar

Julian Vlaiko

Daniel Isaac Goodman

Shahar Bar-Or

Henry Hutton

Danny Berler

Eyal Ittah

Joshua Lehmann

Nian Niles Yang

Mordechai Teicher

Omer Fainzilber

Dudy David Avraham

Eyal Felix Hakoun

Vered Kelner

Itshak Afriat

Noga Deshe

Horst-Christoph Georg Hellwig

Alan David Bennett

Daniel Lee Helmick

Liam Michael Parker

Niles Yang

Amir Shaharabany

Narendhiran Chinnaanangur Ravimohan

Tomer Tzvi Eliash

Nicholas Thomas

Alain Nochimowski

Eldhose Peter

Micha Rave

Peter Grayson

Rakesh Balakrishnan

Einav Zilberstein

Eyal Sobol

Tal Heller

Michael James

Ofer Shapira

Moshe Raz

Mark R Ligameri

Eyal Bychkov

Gautam Ashok Dusija

Rotem Sela

Fabrice Jogand-Coulomb

Stephen Gold

Stella Achtenberg

Kirubakaran Periyannan

Jared Leigh Ficklin

Jason T Lin

Sahil Sharma

Tz-Yi Liu

Mark Shlick

Barry Wright

Ishai Ilani

Rajeev Nagabhirava

Mark Edward Rolston

Ramkumar Ramamurthy

Arseniy Aharonov

Marina Frid

Igor Genshaft

Yoav Markus

Vimal Kumar Jain

Ofir Pele

Alon Eyal

Rami Rom

Yuval Grossman

Amir Segev

Yair Baram

Abhijit K Rao

Uri Peltz

Matias Bjorling

Einat Lev

Yonatan Halevi

Eyal Widder

Daniel Yerushalmi

William Guthrie

Roman Rozental

Avraham Shmuel

A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for device-initiated hibernation

Instead of incorporating a single interface towards the host for transferring data, utilizing a designated write-only storage logging device. The write-only storage logging device can accept sequential streams and automatically overwrite. The controller will read the log material in a secure manner using a different and separate physical connection than the one used for write. The storage device may have LBA ranges that work as write-only as well as other LBA ranges, which are normal (both reads and writes are enabled). Both options will allow for a traditional file system as well as sharing the storage, but will still protect the log areas that would be used for events that should not be read out.

Read-protected storage device with sequential logging

More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Adaptive use of multiple channels in a storage device

A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.

CMB caching using hybrid SRAM/DRAM data path

A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory. In an example embodiment, a memory controller operates to update a logical-to-physical table thereof to change association of physical addresses of sections of user data from being associated with source logical addresses to being associated with destination logical addresses of the host defragmentation requests without moving the user data in the flash memory. Such updates can reduce the number of instances in which the host addresses a non-contiguous logical-address range, which results in a beneficial reduction of the number of input/output commands sent to the data storage device and of the associated processing overhead.

Logical-to-physical mapping for defragmentation of host file system in a data storage device

Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Optimized power up in storage memory devices

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

Write coalescing via HMB to optimize write performance

A controller memory buffer (CMB) is a portion of volatile memory of a controller of a data storage device that is allocated to a host device for use by the host device. When the CMB is not fully utilized, the controller may determine that at least a portion of the unutilized space of the CMB may be used for non-host data. The at least a portion is based on a number of past workloads and a current workload of the CMB. An amount of available space of the CMB that the controller may utilize is dependent on the number of past workloads and the current workload of the CMB. Thus, the volatile memory of the controller may be more optimally utilized.

Excess CMB utilization by storage controller

During data storage device operation, data of multiple blocks of a non-volatile memory device, logically grouped as a jumboblock, may be protected by an exclusive or (XOR) signature, where the XOR signature may be used to recover data of a block of the multiple blocks. During a recovery/relocation operation, data of the jumboblock is read from the non-volatile memory device during the recovery of the lost data and again when the data is relocated. However, because the data read during data storage device operation is temporarily stored in a volatile memory device, the controller utilizes the relevant data stored in the volatile memory device and the data stored in the non-volatile memory device to recover corrupted data. Thus, the amount of reads from the non-volatile memory device decreases due to the relevant data is read from the volatile memory device, which may improve data storage device performance.

Pre-emptive operations for faster XOR recovery and relocation

The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.

Write buffer linking for easy cache reads

When copy commands are queued in a submission queue, there can potentially be many queued input-output (I/O) commands directed to the same logical range as the queued commands. This can result in data being invalidated immediately after it is written in memory, leading to write amplification and inefficient backend processing. To address this problem, the embodiments presented herein can be used to lock the range of logical block addresses of the queued commands, so that I/O commands are prevented from accessing the range of logical block addresses until the queued copy commands are completed.

Data storage device and method for logical range lock

A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is either greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. The sideband is a different communication channel than the PCIe link. The error notification includes additional information regarding events occurring in the data storage device resulting in the quality of the PCIe link.

Content-rich error notification

Instead of a system with no awareness to the specific properties of the described system files, such as atomicity of different types of system files, utilize the special characteristics of the corresponding system files to optimize storage handling. A host marks a certain logical block address (LBA) range as belonging to an atomic file. That entire range will be treated as a single atomic unit. Conversely, an LBA range being used to append to a log file may have very small atomic units, allowing for incremental updates without changing the atomicity of the rest of the media. When a write command is passed, the write command will have a certain length. Depending on the length of the write command, the device can disassemble the write command into smaller write sectors of the smallest possible write portion. The device will then write the small write portions to a storage location, while keeping an atomic principle of each of the small write portions.

SSD optimization awareness to atomicity of different system files

A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

DRAM-less SSD with command draining

In order to guarantee data validity of data read from a memory device of the data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of the decoded data and compare the CRC signature of the decoded data with a CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. Rather than returning an uncorrectable error correction code error (UECC) error to the host device when the CRC signature of the decoded data does not match the CRC signature of the data, the controller executes the read command again. By using a different buffer to store the decoded data, the controller may confirm whether the error stemmed from the read path or the error was not from the read path.

Enhanced end to end system failure recovery

Growing community of inventors

Ofra, Israel

Yehuda Hahn