Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Il Ltd.

Macrovision Corporation

Macrovision Europe Limited

Yehuda Hahn

Shay Benisty

Ariel Navon

Alexander Bazarsky

Ramanathan Muthiah

Alon Marcu

Avichay Haim Hodes

Gadi Vishne

Eran Sharon

Donald Ray Bryant-Rich

Joseph Robert Meza

Daniel Joseph Linnen

Karin Inbar

Daniel Edward Tuers

Hadas Oshinsky

Yacov Duzly

Alex Bazarsky

In-Soo Yoon

Idan Alrod

Julian Vlaiko

Eran Erez

Dmitry Vaysman

Israel Zimmerman

Michael Micha Ionin

Ran Zamir

Itzhak Pomerantz

Abhijeet Manohar

Niles Yang

Daniel Isaac Goodman

Shahar Bar-Or

Henry Hutton

Danny Berler

Eyal Ittah

Joshua Lehmann

Nian Niles Yang

Dudy David Avraham

Mordechai Teicher

Omer Fainzilber

Eyal Felix Hakoun

Vered Kelner

Itshak Afriat

Noga Deshe

Horst-Christoph Georg Hellwig

Alan David Bennett

Daniel Lee Helmick

Liam Michael Parker

Amir Shaharabany

Kirubakaran Periyannan

Narendhiran Chinnaanangur Ravimohan

Tomer Tzvi Eliash

Nicholas Thomas

Eldhose Peter

Alain Nochimowski

Micha Rave

Peter Grayson

Rakesh Balakrishnan

Einav Zilberstein

Eyal Sobol

Tal Heller

Michael James

Ofer Shapira

Omer Gilad

Mark R Ligameri

Eyal Bychkov

Dinesh Kumar Agarwal

Amit Kumar Sharma

Gautam Ashok Dusija

Rotem Sela

Fabrice Jogand-Coulomb

Stephen Gold

Preston Allen Thomson

Stella Achtenberg

Jared Leigh Ficklin

Jason T Lin

Sahil Sharma

Tz-Yi Liu

Mark Shlick

Ishai Ilani

Barry Wright

Rajeev Nagabhirava

Mark Edward Rolston

Amir Segev

Ramkumar Ramamurthy

Marina Frid

Igor Genshaft

Arseniy Aharonov

Ofir Pele

Vimal Kumar Jain

Alon Eyal

Yoav Markus

Rami Rom

Yuval Grossman

Yair Baram

Abhijit K Rao

Matias Bjorling

Uri Peltz

Einat Lev

Sridhar Prudvi Raj Gunda

Yonatan Halevi

Eyal Widder

Systems, methods, and data storage devices for secured failover access through data storage device side channels are described. Storage devices may include a storage interface and one or more side channels, such as control bus and debug bus interfaces. The different interfaces may use different interface protocols and physical interface connections configured for different types of commands to the data storage device. When a failure of the storage interface occurs, the data storage device may receive a failover message through one or more side channels to reconfigure the side channel interface to receive, execute, and return a response for host storage commands targeting host data on the storage medium.

Secured failover access through data storage device side channels

A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.

System and method for flexible emergency power fail management for multiple persistent memory regions

In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to: receive, from a host, a command to read data from the memory, wherein the command comprises a data integrity level threshold; read the data from the memory; determine a data integrity level of the data; in response to the data integrity level of the data being above the threshold, send the data to the host; and in response to the data integrity level of the data not being above the threshold: perform at least one iteration of an error correction operation on the data until the data integrity level of the data is above the threshold; and send the data to the host. Other embodiments are provided, and each of the embodiments can be used alone or in combination.

Data storage device and method for host-managed data integrity

A data storage device and method for enhancing fault tolerance are disclosed. In one embodiment, a method is provided that is performed in a host in communication with first and second data storage devices. The method comprises: determining whether a condition under which primary and secondary copies of data are to be written to the first and second data storage devices, respectively, presents a relatively-high risk of loss of both the primary and secondary copies of the data; and in response to determining that the relatively-high risk is presented, causing the primary and secondary copies of the data to be written differently in the first and second data storage devices, respectively. Other embodiments are provided.

Data storage device and method for enhancing fault tolerance

A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.

Solid-state drive secure data wiping for reuse and recycling

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).

Hybrid address translation cache using DRAM

A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Enhanced digital signal processor (DSP) NAND flash

Instead of ignoring workflow or priority of tenant, modify the write path according to the tenant behavior and system priority using the multi-tenant storage device. When writing information, the write path usually includes RAM memory where the host or device copies the data. The data is copied to the NVM storage element. The RAM memory may be either part of the storage controller (either SRAM or DRAM) or part of the host (like DRAM in HMB) that may be controlled by the storage controller. The RAM memories are used for different goals by the storage controller and optimizing the overall system performance (write/read) is a priority of the storage device. In multi-tenant architectures, the different tenants may have different priorities to have their requirements fulfilled. The tenant priority is passed by the host to the storage device through an interface and either be static or change dynamically during the device operation. Optimizing the write paths according to tenant workload and priority may be done by a module in the storage controller.

Optimizing usage of multiple write paths on multi-tenant storage devices

A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for device-initiated hibernation

Instead of incorporating a single interface towards the host for transferring data, utilizing a designated write-only storage logging device. The write-only storage logging device can accept sequential streams and automatically overwrite. The controller will read the log material in a secure manner using a different and separate physical connection than the one used for write. The storage device may have LBA ranges that work as write-only as well as other LBA ranges, which are normal (both reads and writes are enabled). Both options will allow for a traditional file system as well as sharing the storage, but will still protect the log areas that would be used for events that should not be read out.

Read-protected storage device with sequential logging

More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Adaptive use of multiple channels in a storage device

A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.

CMB caching using hybrid SRAM/DRAM data path

A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory. In an example embodiment, a memory controller operates to update a logical-to-physical table thereof to change association of physical addresses of sections of user data from being associated with source logical addresses to being associated with destination logical addresses of the host defragmentation requests without moving the user data in the flash memory. Such updates can reduce the number of instances in which the host addresses a non-contiguous logical-address range, which results in a beneficial reduction of the number of input/output commands sent to the data storage device and of the associated processing overhead.

Logical-to-physical mapping for defragmentation of host file system in a data storage device

Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Optimized power up in storage memory devices

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

Write coalescing via HMB to optimize write performance

Growing community of inventors

Ofra, Israel

Yehuda Hahn