Macom Technology Solutions Holdings, Inc.

Terayon Communication Systems, Inc.

Applied Micro Circuits Corporation

Texas Instruments Corporation

Macom Connectivity Solutions, LLC

Marvell International Limited

Terayon Communications Systems, Inc.

Other

Broadcom Corporation

Terayon Corporation

Netlogic Microsystems, Inc

Ati Technologies Inc.

Ati International Srl

Sigma Designs, Inc.

Google Technology Holdings LLC

Yehuda Azenkot

Selim Shlomo Rakib

Bart R Zeydel

Zvi Bernstein

Timothy P Walker

Georgios Takos

Manoneet Singh

William Louis Abbott

Nanda Govind Jayaraman

Michael Grosner

Shlomo Selim Rakib

Wee Peng Goh

Gregory Lerner

Simon Pang

Nir Tal

Dan Wolberg

Michael Hellmer

Guy Jacque Fortier

Paul Alan Lind

Michael Grimwood

Brian Abernethy

Michael E Wilhoyte

Amir Michael Fuhrmann

Nanda Govind Jayamaran

Nathalie Anny Tal

Zhenzhong Gu

A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter. The coefficient improvement module is configured to update the coefficients in the lookup table.

Fast equalization for jitter mitigation

System and method of adapting thresholds for constellation selection based on statistic distributions of received data symbols. To determine an adapted threshold, an expected ratio of received symbols with values in a certain range is preset based on an expected statistic distribution of data symbols across the multiple constellations. A first and a second ratios are defined based on the expected ratio, the first ratio being the expected ratio minus an error ratio and the second ratio being the expected ratio plus the error ratio. A first value is determined which makes the received symbols in a firs range to constitute the first ratio of a set of slicer inputs. A second value is determined which makes the received symbols in the second range to constitute the second ratio of a set of slicer outputs. The adapted threshold is then obtained based on the first and the second value.

Constellation selection threshold adaptation for slicer

A system for receiving signals transmitted via serial links includes an analog-to-digital converter configured to sample the first analog signal at a first rate, and generate a first digital input signal having a second data rate. The system also includes a decimator coupled to an output of the equalizer and configured to downsample the first equalized signal to a decimated signal having the first data rate. The system further includes a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a second slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter.

Receiver supporting multiple data rates with fast equalization

An adaptive CTLE used in a receiver with its zero and/or pole frequencies automatically and continuously adjustable based on an error signal and post-cursors. The error signal is derived from the sliced equalized signal that is output from the CTLE. A correction control signal can be determined based on one or more delayed and sampled data (corresponding to the post-cursors) and the error signal. As controlled by the correction control signal, the CTLE zero/pole frequency setting is then adapted such that the CTLE transfer function causes the error signal to decrease while the post cursor ISI is reduced or eliminated. As a result, effective equalization can be advantageously accomplished in a consistent and fast manner.

CTLE adaptation based on post-cursors

System and method of demodulation by adapting constellation values based on statistic distributions of received data symbols. To determine an adapted constellation, an expected ratio of received symbols with values in a certain range is preset based on an expected statistic distribution of data symbols across the multiple constellations. For a set of received symbols, a count ratio of symbols falling in a first range to all the symbols in the set is compared with the expected ratio, where the first range is defined as below a first value. The first value is repeatedly adjusted to adjust the first range until the count ratio equals the expected ratio. The final first value is then designated as the optimal adapted constellation.

Dynamic constellation adaptation for slicer

System and method of timing recovery to achieve sampling phase optimization with aid of equalization adaptation. For equalizer filter, the offset between a current Center of Filter (COF) value and a nominal COF value is used as a measure for a clock phase correction resulted from an adaptive equalization process. A COF may be defined as a function of two selected tap weights or equal to a selected tap weight. The nominal COF value can be dynamically adapted based on the real-time sampling phase error. The tap weights of the equalizer filter are adjusted to decrease the offset, e.g., by interpolating/extrapolating selected tap weights based on the offset. By using sampling phase error as a feedback for COF_nom updating and so for equalization adaptation, the clock delay correction contributed by the adaptive equalization process is advantageously controlled to benefit sampling phase optimization.

Sampling phase optimization for digital modulated signals

A receiver capable of receive and process data signals of multiple baud rates by using an equalizer that is disposed upstream of a decimator. The receiver includes an equalizer coupled to an output of an analog-to-digital converter (ADC), and a decimator couple to the output of the equalizer. The ADC and the equalizer both operate in full rates even in the case of lower data rate, e.g., half or quarter data rate. As the equalizer inherently can inherent remove high frequency noise as well as perform equalization, it practically functions as a low pass filter (LPF). Thereby, there is no need to introduce an extra dedicate LPF upstream of the decimator. This can advantageously and significantly simplify circuitry design and reduce latency.

Receiver supporting multiple data rates

A receiver including an equalizer disposed upstream of a decimator and capable of effectively preventing undesirable interaction between equalization adaptation and the overall timing recovery loop in cases of various data rates. The equalizer operates in a full operation rate even in the case of a lower-than-full data rate, e.g., half or quarter data rate. For input analog signal having 1/M of the full data rate (M&#x3e;1), M or more Center of Filter (COF) values are determine. Each COF may be derived from a function of a respective set of tap weights and compared with a corresponding nominal COF to obtain a COF offset. The resultant COF offsets are used as indications of clock phase correction caused by equalization adaptation to adjust a set of selected tap weights. The taps selected for adjustment encompass at least M samples to correctly indicate the COF offset associate with one symbol.

Mitigating interaction between adaptive equalization and timing recovery in multi-rate receiver

An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/f; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N&#x2212;1)/f, and by a delay of 1/f. The positive sub-DAC and the negative sub-DAC start the conversion at the same time. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of f.

High frequency digital-to-analog conversion by interleaving without return-to-zero

System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

Mitigating interaction between adaptive equalization and timing recovery

System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. Upon a good Signal-to-Noise Ratio (SNR) being achieved, a selected set of the tap weights of the equalizer filter are frozen or set to smaller values, while others continue to adapt and the timing recovery loop continues the clock recovery process. Thereby, the adaptation of equalization can be adjusted to attenuate the equalization filter's effect on clock delay correction by limiting the adaptation time or speed relative to those of the entire timing recovery loop.

An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/f; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N&#x2212;1)/f; and by a delay of 1/f. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of f.

High frequency Digital-to-Analog conversion by interleaving without return-to-zero

An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding first digital input. Two consecutive first digital inputs are shifted by a phase of T=1/f. The second digital inputs are supplied to a set of sub-DACs arrange in parallel. Each sub-DAC operates at a frequency of f/R, and drives an analog output responsive to each second digital input for a duration of R&#xd7;T. Clock signals used by two sub-DACs for converting two consecutive second digital inputs are offset by a phase of T. In each interval of T, summation of the analog signals output from the set of sub-DACs produces an analog value of a single first digital input, thereby achieving a data conversion speed of f.

High frequency digital-to-analog conversion by time-interleaving without return-to-zero

System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

High speed add-compare-select for Viterbi decoder

System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

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Yehuda Azenkot