Freescale Semiconductor,inc.

Freesacle Semiconductor, Inc.

Yehim-Haim Fefer

Sergey Sofer

Valery Neiman

Yoav Weizman

A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.

Device and method for compensating for voltage drops

A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.

Method for testing noise immunity of an integrated circuit and a device having noise immunity testing capabilities

A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage.

A device for testing noise immunity of a circuit includes: an analog circuit, an internal stable reference signal source, an internal power supply module to receive a high level voltage supply, and a signal modulator to provide a noisy signal to the power supply module. The power supply module outputs a noisy power supply to the circuit, in response to the noisy signal, and the device outputs a signal representative of a noise immunity of the circuit. A method includes: providing a high level supply voltage to an internal power supply module, receiving signals representative of the performance of an analog circuit, providing a noisy signal to an input of the power supply module, providing a noisy supply voltage to the circuit, by the power supply module, in response to the noisy signal, and evaluating a noise immunity characteristic of the circuit in response to the received signals.

Device and method for testing a noise immunity characteristic of analog circuits

A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.

Growing community of inventors

Petah-Tikva, Israel

Yehim-Haim Fefer