Integrated Device Technology, Inc.

Yehayahu Mor

Philip A Bourekas

Avigdor Willenz

A structure and a method are provided to implement a memory bus arbiter, in which separate priorities are provided to instruction and data reads from the main memory. In one embodiment in a microprocessor with an on-chip cache, the present invention provides an arbiter which yields the memory bus, in decreasing priority order, to an ongoing bus transaction, a 'direct memory access' (DMA) request, an instruction read resulting from a cache miss, a pending write request, and a read request, including reference to an uncacheable portion of memory and a data cache miss.

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Cupertino, CA, United States of America

Yehayahu Mor