Vanguard International Semiconductor Corporation

National Yang Ming Chiao Tung University

Yeh-Jen Huang

Jian-Hsing Lee

Hwa-Chyi Chiou

Wen-Hsin Lin

Yeh-Ning Jou

Chun-Jung Chiu

Chia-Wei Hung

Shin-Cheng Lin

Li-Yang Hong

Shu-Ling Chang

Fu-Hsin Chen

Ming-Dou Ker

Geeng-Lih Lin

Yu-Hao Ho

Wen-Yi Chen

A semiconductor device includes a gate electrode disposed on a substrate. A source region and a drain region are disposed in the substrate and located on two sides of the gate electrode respectively. The drain region includes a plurality of drain segments that are laterally separated from each other. These drain segments have a first conductive type and the substrate has a second conductive type. A plurality of drain contacts is electrically connected to the drain segments. Each drain segment corresponds to at least one of these drain contacts. A drain electrode is electrically connected to these drain contacts. A source electrode is electrically connected to the source region.

Semiconductor device

An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.

Electronic device and electrostatic discharge protection circuit

A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.

Control circuit and high electron mobility element

A semiconductor device including a substrate, a seed layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source/drain structure, a second source/drain structure, and a contact is provided. The seed layer is disposed on the substrate. The buffer layer is disposed on the seed layer. The channel layer is disposed on the buffer layer. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The first and second source/drain structures are disposed on opposite sides of the gate structure. The contact contacts the first source/drain structure. The distance between the gate structure and the contact is between 0.5 micrometers and 30 micrometers.

Semiconductor device and operation circuit

An electrostatic discharge protection device including a substrate, a first PNP element, a second PNP element, and an isolation region is provided. The substrate has a P-type conductivity. The first and second PNP elements are formed in the substrate. The isolation region isolates the first and second PNP elements.

Electrostatic discharge protection device

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.

Semiconductor device structures

A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer.

High-voltage LDMOSFET devices having polysilicon trench-type guard rings

An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively.

An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

Growing community of inventors

Hsinchu, Taiwan

Yeh-Jen Huang