International Business Machines Corporation

Yee-Ming Ting

Donald W Price

John Ulrich Knickerbocker

Govindarajan Natarajan

Jon Alfred Casey

Raschid Jose Bezama

Lester W Herron

Shaji Farooq

Donald Rene Wall

Mario E Ecker

Vivek M Sura

David H Gabriels

Giai V Yen

William K Rodiger

John Thomson

Sharon L Tracy

Robert M Troncillito

Irene S Frantz

Sarah Huffsmith Knickerbocker

Dale E Pontius

Michael Ignatowski

Lishing Liu

Billy J Knowles

Robert Tamlyn

Matthew A Krygowski

Gregory Salyer

Patrick M Gannon

Warren W Grunbok

Sara H Knickerbocker

William R Milani

De Tran

Henry Yeh

Katharine G Frase

Jon E Thorson

Katherine G Frase

Michael P Witt

Douglas R Moran

A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.

Large ceramic article and method of manufacturing

Large ceramic articles and method of manufacturing

A two-level multiple bit error correction scheme includes at the first level a memory chip with a memory error detection capability that produces a chip error signal (CES) when it detects errors in the bits leaving that chip and at the second level an off-chip ECC facility which interprets generated syndrome bits and chip error signals in order to determine which bits are bad. There are two types of codes distinguished by the absence or presence of parity bits. The use of parity bits allows for the detection of single bit errors in data read from the chip. Therefore, the CES is active only for detected multiple bit errors. Chips not using parity bits are less expensive, but the CES must be active for both single bit and multiple bit errors.

Synergistic multiple bit error correction for memory of array chips

A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

Memory system and unique memory chip allowing island interlace

A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

Coherence control by data invalidation in selected processor caches

An N.times.M matrix adapted to couple N inputs from N processor to M basic storage modules is disclosed. The system includes arbitrators and gating means for each output responsive to request signals for simultaneously coupling data from a plurality of processors to requested basic storage modules under arbitrator control.

N.times.M round robin order arbitrating switching matrix system

Growing community of inventors

Cornwall, NY, United States of America

Yee-Ming Ting