Altera Corporation

Yee Liang Tan

Chooi Pei Lim

Siang Poh Loh

Keong Hong Oh

Kar Keng Chua

Jayabrata Ghosh Dastidar

Jun Pin Tan

Jordan Plofsky

Teik Tiong Toong

Siew Ling Yeoh

Chiew Khiang Kuit

Siang Poh Lob

Kok Sun Chia

Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Multi-layer distributed network

Integrated circuit packages with a signal routing control through a given direction are disclosed. A disclosed integrated circuit package includes a plurality of interconnects. A first logic circuitry of a first integrated circuit may produce a first signal that may be transmitted to a second integrated circuit. The integrated circuit package further includes interconnect circuitry disposed between the first and second integrated circuits. Multiplexing circuitry may select the first signal from second logic circuitry when the first logic circuitry is defective and may direct the signal as output signal to the second integrated circuit through a given interconnect.

Method and apparatus for providing signal routing control

Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

Systems including an I/O stack and methods for fabricating such systems

Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.

Integrated circuit with configurable test pins

Growing community of inventors

Gelugor, Malaysia

Yee Liang Tan