International Business Machines Corporation

Dell Products Inc.

Yee Ja

Bradley Nelson

Marshal F Savage

Cyril Jose

Wolfgang Roesner

Chandrasekhar Puthillathe

Robert Benjamin Gass

Choudary Maddukuri

Christoph Jaeschke

Zoltan T Hidvegi

Bing-Lun Chu

Jason Raymond Baumgartner

Viresh Paruthi

Hari Mony

Anto DolphinJose Jesurajan Marystella

Farhan Mohammed Syed

Srihari Srirangam

Barinjato Ramanandray

Thi D Hyunh

A system for distributing firmware, comprising a group controller operating on a processor and configured to perform an algorithmic process of sending an update task with a download host to one of two or more group members. A group member operating on a processor and configured to perform an algorithmic process of receiving the update task with the download host and to request a payload file from the download host.

System and method for providing an intelligent ephemeral distributed service model for server group provisioning

Methods and systems for access in a management controller group hierarchy may involve receiving a request for a user at an information handling system, determining whether a link of trust is established, and validating the single sign-on request. The request may be to authenticate the user for access using a single sign-on token. Determination of whether the link of trust is established may be based on an initial login location stored in the single sign-on token. Validation of the single sign-on token may be based on a determination that the link of trust is established.

System and method for group of groups single sign-on demarcation based on first user login

Methods and systems for providing quality of service to an information handling system may involve generating a new transport encryption key for a management controller group, notifying nodes in the management controller group to negotiate for the new transport encryption key, and encrypting a first message to be sent to a first node in the management controller group using a current transport encryption key. The new transport encryption key for encrypted communications in the management controller group and to replace a current transport encryption key. The first message encrypted after notifying the nodes in the management controller group to negotiate for the new transport encryption key. The nodes of the management controller group including the first node.

System and method for providing quality of service during transport key rotation at a distributed management controller group

Methods and systems for account authentication in a distributed computing node group may involve sending a message to a member, the message having a first timestamp, increasing an authentication failure count, receiving a first key-exchange message from the member, the first key-exchange message having a second timestamp, evaluating the second timestamp, and determining whether to ignore the first key-exchange message based on an evaluation of the second timestamp. The first timestamp may be associated with a message received from the member prior to sending the message with the first timestamp to the member. The first key-exchange message may include a value computed by the member based on a group passcode shared with the member. The evaluation of the second timestamp may be based on at least one of a default value, the authentication failure count, or a timestamp associated with the group passcode.

System and method for preventing well behaving clients from causing account lockouts in a group

Methods and systems for managing distributed group identity may involve exchanging, at a node in a group, node identifiers with another node in the group, sorting the node identifiers, selecting an identifier from the sorted identifier, proposing the selected identifier as a persistent group name, setting the persistent group name based on the proposed identifier, setting a user administered name based on the proposed identifier, determining that the user administered name is consistent across the group, and updating the user administered name to resolve the inconsistency. The persistent group name is common across the group.

System and method for managing distributed cluster identity

Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.

Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic

Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may than alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, chances to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

Methods and arrangements to model an asynchronous interface

An apparatus and computer program product for driving values to 'don't care' (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Driving values to DC adjusted/untimed nets to identify timing problems

Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

Modeling asynchronous behavior from primary inputs and latches

Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Sequential equivalence checking for asynchronous verification

Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

Accurately modeling an asynchronous interface using expanded logic elements

A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along the coincident portions to form non-intersecting, separate paths from the receive latch to two or more sinks. Common data or control inputs are provided for the gates in the replicated combinational logic. Driver logic may additionally be inserted along each replicated path, upstream of the combinational logic, to independently drive each of the sinks.

Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation

A method for propagating phase constants for static circuit model analysis is provided. The mechanisms of the illustrative embodiments make use of multiple phases of constant propagation to handle sequential elements in a circuit model. The phases are determined based on an oscillating clock input. In one exemplary embodiment, the number of phases is determined based on a least common denominator of the periodicity of the input clocks of nets in the circuit model. The static analysis is performed for each phase taking into consideration the results of a previous phase of the static analysis with regard to sequential elements of the circuit. Results may be output for verification of the circuit design.

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Round Rock, TX, United States of America

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