Taiwan Semiconductor Manufacturing Comp. Ltd.

Yee-Chia Yeo

Huicheng Chang

Chenming Hu

Fu-Liang Yang

Liang-Yin Chen

Chih Chieh Yeh

Hung-Li Chiang

Cheng-Yi Peng

Su-Hao Liu

Wen-Chin Lee

Chun-Chieh Lin

Ling-Yen Yeh

Jyh-Cherng Sheu

Chii-Horng Li

Chih-Sheng Chang

Chih-Hsin Ko

Li-Li Su

Chi-Wen Liu

Kuo-Ju Chen

Tung Ying Lee

Hsueh-Chang Sung

Carlos H Diaz

Pei-Ren Jeng

Chien-Chao Huang

Cheng-Hsien Wu

Li-Ting Wang

Chia-Cheng Chen

Meng-Hsuan Hsiao

Szu-Ying Chen

I-Sheng Chen

Chih-Chieh Yeh

Yu-Lin Yang

Chi On Chui

Ziwei Fang

Chun-Feng Nieh

Yen-Ming Chen

Chao-Hsiung Wang

Ming-Hua Yu

Jean-Pierre Colinge

De-Wei Yu

Hung-Ming Chen

Chih-Hao Wang

Sung-Li Wang

Liang-Gi Yao

Yu-Chang Lin

Chih-Kai Yang

Chien-I Kuo

Chun-Hung Wu

Mong-Song Liang

Tsung-Lin Lee

Chung-Cheng Wu

Yen-Ru Lee

Syun-Ming Jang Jang

Tzu-Chiang Chen

Ping-Wei Wang

Chien-Hung Chen

Xiong-Fei Yu

Chia-Cheng Ho

Teng-Chun Tsai

Shih-Chang Chen

Kei-Wei Chen

Weng Chang

Chan-Lon Yang

Tsz-Mei Kwok

Chun-Hsien Huang

Wen-Hsing Hsieh

Tsan-Chun Wang

Wilman Tsai

Yu-Ming Lin

Wei-Yang Lee

Zhiqiang Wu

Chih-Chiang Chang

Chih-Wei Chang

Ying-Lang Wang

Kuo-Nan Yang

Yasutoshi Okuno

Chien-Hao Chen

Ta-Pen Guo

Chia-Pin Lin

Blandine Duriez

Kai-Hsuan Lee

Martin Christopher Holland

Cheng-Tung Lin

Ken-Ichi Goto

Chun-Yen Chang

Chien-Chang Su

Chi-On Chui

Ya Hui Chang

Chien-Tai Chan

Huang-Yi Huang

Yuan-Hung Chiu

Jeng-Ya David Yeh

Horng-Huei Tseng

Yung-Cheng Lu

Tai-Chun Huang

Chao-Ching Cheng

Pang-Yen Tsai

Wei-Yuan Lu

Shen-Nan Lee

Shien-Yang Wu

In an embodiment, a device includes: a source/drain region adjacent a channel region; an inter-layer dielectric on the source/drain region; a source/drain contact extending through the inter-layer dielectric and into the source/drain region; a metal-semiconductor alloy region between the source/drain contact and the source/drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source/drain contact, the contact spacer including the first dopant and an amorphizing impurity.

Transistor source/drain contacts and methods of forming the same

In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

Methods of forming transistor source/drain regions comprising carbon liner layers

In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

Transistor isolation regions and methods of forming the same

A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.

Nanostructure FET and method of forming same

A method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region; forming a plurality of trenches in the first region of the substrate; forming a multi-layer stack over the substrate and in the trenches; and patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, where the multi-layer stack includes at least one of first semiconductor layers and at least one of second semiconductor layer stacked alternately, and the plurality of trenches are in corresponding ones of the first fins.

Methods of forming alignment structure with trenches for semiconductor devices

A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

Apparatus, system, and method for measuring the temperature of a substrate

A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.

Method for forming semiconductor device with monoclinic crystalline metal oxide capping layer

A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.

Nano-structure transistors with air inner spacers and methods forming same

A semiconductor device including a seeding layer in the source/drain region and a method of forming is provided. The semiconductor device may include a plurality of nanostructures over a substrate, a gate structure wrapping around the plurality of nanostructures, a source/drain region adjacent the plurality of nanostructures, and inner spacers between the source/drain region and the gate structure. The source/drain region may include a polycrystalline seeding layer covering sidewalls of the plurality of nanostructures and sidewalls of the inner spacers, and a semiconductor layer over the seeding layer. The semiconductor layer may have a higher dopant concentration than the seeding layer.

Semiconductor device and method

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a position of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Wafer positioning method and apparatus

A method includes moving a plurality of sensors along a translation path with respect to an ion beam, acquiring sensor signals produced by the plurality of sensors, converting the acquired sensor signals into a data set representative of a two-dimensional (2D) profile of the ion beam, generating a plurality of first one-dimensional (1D) profiles of the ion beam from the data set, generating a plurality of second 1D profiles of the ion beam by spatially inverting each of the plurality of first 1D profiles, generating a plurality of third 1D profiles of the ion beam by superposing first current density values of each of the plurality of first 1D profiles with second current density values of a corresponding one of the plurality of second 1D profiles and determining whether to continue an implantation process with the ion beam in accordance with the plurality of third 1D profiles.

Method for ion implantation uniformity control

In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

Semiconductor device and method of forming same

The present disclosure provides a substrate bonding apparatus capable of temperature monitoring and temperature control. The substrate bonding apparatus comprises a fluid cooling module and a sensor module for detecting temperatures at multiple zones (e.g., two or more zones) within a substrate. The substrate bonding apparatus according to the present disclosure achieves temperature stabilization within the substrate. The substrate bonding apparatus further improves bonding process performance by reducing distortion residual, reducing bubbles on edges of the substrate, and reducing non-bonded area within the substrate.

Temperature controllable bonder equipment for substrate bonding

A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.

Method of forming source/drain regions with quadrilateral layers

A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

Laser de-bonding carriers and composite carriers thereof

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Hsinchu, Taiwan

Yee-Chia Yeo