Taiwan Semiconductor Manufacturing Comp. Ltd.

Yee-Chia Yeo

Huicheng Chang

Chenming Hu

Fu-Liang Yang

Liang-Yin Chen

Chih Chieh Yeh

Hung-Li Chiang

Cheng-Yi Peng

Su-Hao Liu

Wen-Chin Lee

Chun-Chieh Lin

Jyh-Cherng Sheu

Ling-Yen Yeh

Chii-Horng Li

Chih-Sheng Chang

Chih-Hsin Ko

Li-Li Su

Chi-Wen Liu

Kuo-Ju Chen

Tung Ying Lee

Hsueh-Chang Sung

Li-Ting Wang

Carlos H Diaz

Cheng-Hsien Wu

I-Sheng Chen

Pei-Ren Jeng

Chien-Chao Huang

Szu-Ying Chen

Chia-Cheng Chen

Meng-Hsuan Hsiao

Chi On Chui

Chun-Feng Nieh

Chih-Chieh Yeh

Yu-Lin Yang

Ziwei Fang

Yen-Ming Chen

Chao-Hsiung Wang

Ming-Hua Yu

Chien-I Kuo

Jean-Pierre Colinge

Sung-Li Wang

Yu-Chang Lin

De-Wei Yu

Hung-Ming Chen

Chih-Hao Wang

Liang-Gi Yao

Chih-Kai Yang

Chun-Hung Wu

Mong-Song Liang

Tsung-Lin Lee

Chung-Cheng Wu

Yen-Ru Lee

Syun-Ming Jang Jang

Wei-Yang Lee

Tzu-Chiang Chen

Ping-Wei Wang

Chien-Hung Chen

Xiong-Fei Yu

Chia-Cheng Ho

Teng-Chun Tsai

Kei-Wei Chen

Shih-Chang Chen

Weng Chang

Chan-Lon Yang

Tsz-Mei Kwok

Chun-Hsien Huang

Wen-Hsing Hsieh

Tsan-Chun Wang

Wilman Tsai

Yu-Ming Lin

Zhiqiang Wu

Chih-Chiang Chang

Chih-Wei Chang

Ying-Lang Wang

Tai-Chun Huang

Kuo-Nan Yang

Yasutoshi Okuno

Chien-Hao Chen

Ta-Pen Guo

Chia-Pin Lin

Blandine Duriez

Kai-Hsuan Lee

Martin Christopher Holland

Cheng-Tung Lin

Ken-Ichi Goto

Chun-Yen Chang

Chien-Chang Su

Chi-On Chui

Ya Hui Chang

Chien-Tai Chan

Huang-Yi Huang

Jeng-Ya David Yeh

Yuan-Hung Chiu

Horng-Huei Tseng

Yung-Cheng Lu

Chao-Ching Cheng

Pang-Yen Tsai

Wei-Yuan Lu

Shen-Nan Lee

Shien-Yang Wu

A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes

A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface the (110)-orientated substrate and extending in a <10> direction perpendicular to the <110> direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Semiconductor device having multi-layer epitaxial structures with different lattice constants

A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

Shallow trench isolation forming method and structures resulting therefrom

A method of manufacturing a semiconductor device includes: determining a first reflectivity of a first anneal region on a wafer; determining a second reflectivity of a second anneal region on the wafer, performing a first laser shot on the first anneal region, measuring a first temperature of the first anneal region, and performing a second laser shot on a second anneal region. A power of the first laser shot is set in accordance with the first reflectivity. A power of the second laser shot is set in accordance with the second reflectivity.

Systems, methods, and semiconductor devices

A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Multi-gate device and method of fabrication thereof

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Trench filling through reflowing filling material

A method includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. The second wafer is brought into physical contact with the first wafer. A relative distance between the first wafer and the second wafer is monitored using a distance sensor. A pressure of a vacuum zone on the second wafer chuck is controlled using feedback from the distance sensor. The bonded first wafer and second wafer are removed from the first wafer chuck.

Bonding system and method for using the same

A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

Integrated circuit structure

A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.

Semiconductor device and method of manufacture

In an embodiment, a device includes: a source/drain region adjacent a channel region; an inter-layer dielectric on the source/drain region; a source/drain contact extending through the inter-layer dielectric and into the source/drain region; a metal-semiconductor alloy region between the source/drain contact and the source/drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source/drain contact, the contact spacer including the first dopant and an amorphizing impurity.

Transistor source/drain contacts and methods of forming the same

In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

Methods of forming transistor source/drain regions comprising carbon liner layers

In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

Transistor isolation regions and methods of forming the same

A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.

Nanostructure FET and method of forming same

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Hsinchu, Taiwan

Yee-Chia Yeo