Taiwan Semiconductor Manufacturing Comp. Ltd.

Taiwan Semiconductor Manufacturing Co., Ltd.

Yee-Chia Yeo

Huicheng Chang

Chenming Hu

Fu-Liang Yang

Liang-Yin Chen

Chih Chieh Yeh

Hung-Li Chiang

Cheng-Yi Peng

Su-Hao Liu

Wen-Chin Lee

Chun-Chieh Lin

Jyh-Cherng Sheu

Ling-Yen Yeh

Chii-Horng Li

Chih-Sheng Chang

Li-Li Su

Chih-Hsin Ko

Chen-Fong Tsai

Chi-Wen Liu

Li-Ting Wang

Kuo-Ju Chen

Hao-Yu Chen

Wei-Min Liu

Tung Ying Lee

Hsueh-Chang Sung

Sen-Hong Syue

Carlos H Diaz

Cheng-Hsien Wu

Szu-Ying Chen

I-Sheng Chen

Pei-Ren Jeng

Chien-Chao Huang

Han-De Chen

Chia-Cheng Chen

Meng-Hsuan Hsiao

Meng-Han Chou

Chi On Chui

Ming-Hua Yu

Chun-Feng Nieh

Chih-Chieh Yeh

Yu-Lin Yang

Chien-Wei Lee

Tsai-Yu Huang

Ziwei Fang

Yun Chen Teng

Yen-Ming Chen

Chao-Hsiung Wang

Chien-I Kuo

Wen-Yen Chen

Che-Yu Lin

Jean-Pierre Colinge

Sung-Li Wang

Yu-Chang Lin

Hung-Ming Chen

De-Wei Yu

Wei-Ting Chien

Szu-Wei Huang

Chih-Hao Wang

Liang-Gi Yao

Chih-Kai Yang

Chun-Hung Wu

Yuan-Chen Sun

Mong-Song Liang

Tsung-Lin Lee

Chung-Cheng Wu

Yen-Ru Lee

Yi-Fang Pai

Chung-Hu Ke

Tsung-Yao Wen

Wei Hao Lu

Tien-Shun Chang

Chen Ming Hu

Tz-Shian Chen

Syun-Ming Jang Jang

Wei-Yang Lee

Tzu-Chiang Chen

Ping-Wei Wang

Chien-Hung Chen

Tsz-Mei Kwok

Xiong-Fei Yu

Chia-Cheng Ho

Heng-Wen Ting

Jeng-Wei Yu

Tsung-Hsi Yang

Chien-Hsing Lee

Chia-Wen Chang

Hsun-Chih Tsao

Chuan-Yi Lin

Hong-Nien Lin

Jung-Jen Chen

Po-Kai Hsiao

Cheng-I Chu

Han-Yu Tang

Cheng-Yen Wen

Teng-Chun Tsai

Kei-Wei Chen

Shih-Chang Chen

Weng Chang

Chan-Lon Yang

Chia-Pin Lin

In an embodiment, a device includes: a semiconductor fin extending from a semiconductor substrate; a nanostructure above the semiconductor fin; a source/drain region adjacent a channel region of the nanostructure; a bottom spacer between the source/drain region and the semiconductor fin; and a gap between the bottom spacer and the source/drain region.

Transistor source/drain regions and methods of forming the same

A method for manufacturing a semiconductor device includes: forming a first type well in a substrate; and after forming the first type well in the substrate, forming a second type well in the substrate, where the second type well has a conductivity type different from that of the first type well. One of the first and second type wells is formed by sequentially performing multiple ion implantations that use different energies, and one of the ion implantations that uses a lowest energy among the ion implantations is performed first among the ion implantations.

Method for forming wells for semiconductor devices using implanations of increasing energy

A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.

Method of manufacturing semiconductor devices having metal gate structure and semiconductor devices

In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.

Semiconductor device and method of manufacture

A method includes: transporting a wafer to an apparatus, the apparatus including: a first chamber configured to receive the wafer and a first gas; a second chamber surrounding the first chamber and configured to receive a second gas; a plurality of gas inlets on a chamber wall of the second chamber; and a plurality of gas vents on the chamber wall of the second chamber; heating the first chamber while keeping a gas pressure difference between the first chamber and the second chamber within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit.

Annealing apparatus and method of operating the same

In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.

Apparatus and method for use with a substrate chamber

A method of forming a semiconductor device includes forming a first dummy gate structure over a first region of a substrate and a second dummy gate structure over a second region of the substrate, the first region and the second region of the substrate having a first composition, the first composition having a first etch rate; implanting the first region of the substrate with dopants laterally adjacent to the first dummy gate structure, wherein after the implanting the first region, the first region has a second composition having a second etch rate, the second etch rate being different from the first etch rate; etching a first recess in the first region of the substrate having the second composition and a second recess in the second region having the first composition; and epitaxially growing a first source/drain region in the first recess and a second source/drain region in the second recess.

Semiconductor device and methods of forming the same

A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes

A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface the (110)-orientated substrate and extending in a <10> direction perpendicular to the <110> direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Semiconductor device having multi-layer epitaxial structures with different lattice constants

A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

Shallow trench isolation forming method and structures resulting therefrom

A method of manufacturing a semiconductor device includes: determining a first reflectivity of a first anneal region on a wafer; determining a second reflectivity of a second anneal region on the wafer, performing a first laser shot on the first anneal region, measuring a first temperature of the first anneal region, and performing a second laser shot on a second anneal region. A power of the first laser shot is set in accordance with the first reflectivity. A power of the second laser shot is set in accordance with the second reflectivity.

Systems, methods, and semiconductor devices

A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Multi-gate device and method of fabrication thereof

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

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Hsinchu, Taiwan

Yee-Chia Yeo