Taiwan Semiconductor Manufacturing Comp. Ltd.

Yean-Zhaw Chen

I-Hsiu Wang

Yi-Wei Chiu

Cheng-Wei Chang

Yu Shih Wang

Wan Hsuan Hsu

Chun-Chih Cheng

Ying-Ting Hsia

Hsin-Yan Lu

Jhao-Ping Jiang

Chen-Shien Chen

Kai-Hsiung Chen

Yih-Shung Lin

Yai-Yei Huang

A semiconductor device includes a semiconductor substrate, a pair of source/drain regions on the semiconductor substrate, and a gate structure on the semiconductor substrate and between the pair of source/drain regions. The gate structure includes a first metal layer and a second metal layer in contact with the first metal layer. A sidewall of the first metal layer and a top surface of the semiconductor substrate form a first included angle, a sidewall of the second metal layer and the top surface of the semiconductor substrate form a second included angle. The second included angle is different from the first included angle.

Semiconductor device and method for manufacturing the same

An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

Contact structure and method of fabricating the same

A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion.

A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.

A one-time feedback CMP process control method which contributes to uniformity in the quantity of material removed from wafers in a lot during semiconductor processing and is suitable for complex processes such as STI (shallow trench isolation) fabrication procedures, is disclosed. The method includes providing a plurality of wafers having a set of pilot wafers and a set of remaining wafers, polishing each of the pilot wafers according to an original process time, determining a compensation time for the pilot wafers, determining an update time by adding the compensation time to the original process time and polishing the set of remaining wafers according to the update time.

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Tainan, Taiwan

Yean-Zhaw Chen