Altera Corporation

Yean-Yow Hwang

Richard Yuan

Michael David Hutton

Babette Van Antwerpen

Bruce B Pedersen

David Wolk Mendel

Gregg William Baeckler

Boris Ratchev

Joachim Pistorius

A method for designing systems on field programmable gate arrays (FPGAs) includes caching design information from a compilation of a system design. The design information is utilized in a compilation of a subsequent system design.

Method and apparatus for facilitating an adaptive electronic design automation tool

A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.

Physical resynthesis of a logic design

Techniques for mapping functions in a user design to lookup tables on a programmable integrated circuit are provided. Functions within a user design are rewritten as a composition of smaller, decomposed functions using a decomposition technique. An attempt is made to fit the decomposed functions into a lookup table configuration. If the decomposed functions do not fit into one the lookup table configurations for the programmable integrated circuit, the input variables are rotated within the user function. Then, an attempt is made to decompose the user function again based on the rotated input variables.

Techniques for mapping functions to lookup tables on programmable circuits

A computer aided system includes a method of improving the accuracy, optimization, and minimization for the synthesis and mapping of logical functions into the logical structures of a target technology, such as the logic cells (e.g., look-up tables) of a programmable logic integrated circuit. In a specific implementation, the invention incorporates late-stage synthesis operations, such as found during a technology mapping operation, into earlier stage synthesis procedures. These late-stage synthesis operations are used to provide better estimates of delay and area of a final compiled design in order to guide optimization operations.

Estimating quality during early synthesis

A technique of minimizes circuit area on programmable logic with fracturable logic elements by using 'balancing' in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.

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Palo Alto, CA, United States of America

Yean-Yow Hwang