Sandisk Information Technology (shanghai) Co., Ltd.

Western Digital Technologies, Inc.

Ye Bai

Chin-Tien Chiu

Kaiyou Qian

Hem P Takiar

Chih-Chin Liao

Shineng Ma

Dacheng Huang

Lei Shi

Cheeman Yu

Zhong Lu

Ting Liu

Yazhou Zhang

Yangming Liu

Chin Tien Chiu

Binbin Zheng

Cheng-Hsiung Yang

Yanwen Bai

JinXiang Huang

Songtao Lu

Peng Fu

Yuequan Shi

Shan Luo

Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.

Printed circuit board trace for galvanic effect reduction

A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Semiconductor device including control switches to reduce pin capacitance

A semiconductor device is disclosed including a stack of wafers having a densely configured 3D array of memory die. The memory die on each wafer may be arranged in clusters, with each cluster including an optical module providing an optical interconnection for the transfer of data to and from each cluster.

Semiconductor device including optically connected wafer stack

A semiconductor device is disclosed including material for absorbing EMI and/or RFI. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die. The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer on the substrate, or within a dielectric core of the substrate. The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.

Semiconductor device including electromagnetic absorption and shielding

A semiconductor device is disclosed including material for absorbing EMI and/or RFI The device includes a substrate (), one or more semiconductor die (), and molding compound around the one or more semiconductor die (). The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer () on the substrate (). The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.

A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed. The metallic layer is formed on a metallic layer transfer assembly. The metallic layer transfer assembly and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the metallic layer is transferred from the shield to the encapsulated memory device.

EMI shielding and thermal dissipation for semiconductor device

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Shanghai, China

Ye Bai