Western Digital Technologies, Inc.

Henkel Ag & Company, Kgaa

Sandisk Information Technology (shanghai) Co., Ltd.

Yazhou Zhang

Chin-Tien Chiu

Jiandi Du

Hope Chiu

Cong Zhang

Shineng Ma

Binbin Zheng

Wenbin Qu

Sundarraj Chandran

Jing Yang

Chih-Chin Liao

Yangming Liu

Xuyi Yang

Zengyu Zhou

Anja Henckens

Ye Bai

Fen Yu

Yanwen Bai

Paul Qu

Kent Yang

Yifan Chen

Honny Chen

Ada Shen

Gary Zheng

Elisabeth Theunissen

The present invention relates to an electrically conductive composition comprising a silicone resin comprising at least one vinyl-group; a silicone cross-linker having at least one Si—H group; electrically conductive particles; a solvent; an adhesion promoter; a catalyst; and an inhibitor, wherein ratio between Si—H groups and vinyl-groups is equal or greater than 1.3 but equal or less than 10.

Electrically conductive silicone composition with high adhesion strength

A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.

Semiconductor device package die stacking system and method

A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.

Thermoelectric semiconductor device and method of making same

A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.

Flip-chip package with reduced underfill area

A semiconductor device package includes a substrate, a first heat-generating component positioned on a surface of the substrate, an encapsulant at least partially encapsulating the first heat-generating component, and one or more channels extending through a portion of the encapsulant toward the first heat-generating component. Each of the one or more channels contains a thermally conductive material having a thermal conductivity greater than a thermal conductivity of the encapsulant.

Semiconductor device package having thermally conductive pathways

A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.

Semiconductor device package having thermally conductive layers for heat dissipation

A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.

Semiconductor die and semiconductor package

A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.

Multi-module integrated interposer and semiconductor device formed therefrom

A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Semiconductor device including control switches to reduce pin capacitance

A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.

Semiconductor device including high speed heterogeneous integrated controller and cache

A semiconductor device is disclosed including a stack of semiconductor die. Openings are formed in the semiconductor die as they are added to the stack, which openings are aligned at different levels of the stack. The openings are filled with an electrically insulative compound to form a molded column through all semiconductor die in the stack. After all semiconductor die are added to the stack, a via may be drilled through the molded column to electrically interconnect each semiconductor die in the stack.

Growing community of inventors

Shanghai, China

Yazhou Zhang