Huazhong University of Science and Technology

Huawei Technologies Co., Limited

Yaxiong Zhou

Xiangshui Miao

Yi Bu Li

Junfeng Zhao

Tao Zhang

Huajun Sun

Zhulin Wei

Ronggang Xu

Long Cheng

Qun Liu

Tianpeng Miao

Zhuorui Wang

The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Computing array based on 1T1R device, operation circuits and operating methods thereof

A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M&#x2212;1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.

Memristor-based processor integrating computing and memory and method for using the processor

A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

Method, apparatus and device for operating logical operation array of resistive random access memory

A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M, the second resistive switching element Mincluding a positive electrode and a negative electrode. The negative electrode of the first resistive switching element Moperates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element Moperates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element Mis connected to the positive electrode of the first resistive switching element M, and a connected end thereof operates as the output end of the logic operation circuit.

Non-volatile boolean logic operation circuit and operation method thereof

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Wuhan, China

Yaxiong Zhou