Intel Corporation

Qualcomm Incorporated

Topside Research, LLC

Yaxin Shui

James W Tschanz

Daniel Nemiroff

Keith D Underwood

Jonathan M Eastep

Carlos Alfonso Tokunaga

Federico Ardanaz

Minki Cho

Bao K Vuong

Kah Meng Yeem

Phil Terry

Siddhartha Jana

Kevin Robertson

Quang Hong

An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

Detecting laser-injected faults

Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.

System-wide network activity forecasting for performance improvement

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A configurable clock tree includes a delay matrix that may be configured such that each the timing of clocks for each of a plurality of data lanes can be optimized for minimum skew. Selections between different versions of a base clock signal and different paths available to the selected version may provide a root clock used for transmitting data on a communications link. The versions of the one or more clock signals may include three versions of a first clock signal. Each version of the first clock signal may be subject to a different delay with respect to the clock signal.

Configurable clock tree

There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned.

Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices

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San Diego, CA, United States of America

Yaxin Shui