Kabushiki Kaisha Toshiba

Yauto Sumi

Wataru Saito

Syotaro Ono

Hiroshi Ohta

Masaru Izumisawa

Masakatsu Takashita

Wataru Sekine

Shoichiro Kurushima

A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.

Power semiconductor device

Growing community of inventors

Hyogo-ken, Japan

Yauto Sumi