Skhynix Inc.

Yauheni Yaromenka

Siarhei Zalivaka

Teodor Vlasov

Aliaksei Charnevich

Joon Mo Koo

A data processing system includes a host, a plurality of memory devices configured to operate in parallel and a controller including a host interface controller and a plurality of cores, which are respectively coupled to the plurality of memory devices. The controller splits a logical block address (LBA) range associated with each of the cores into a plurality of LBA groups. When it is detected that there is imbalance of workloads among the cores, the controller identifies first and second cores contributing to the imbalance of workloads and selects a first LBA group, among the range of LBAs of the first core, and selecting a second LBA group, among the range of LBAs of the second core. The controller transfers data associated with the first LBA group to the second LBA group and reroutes data initially intended for the first LBA group to the second LBA group.

Systems and methods for dynamic logical block address distribution between multicores

Memory systems and components thereof perform clustering on workload items. Such a memory system comprises a memory device from which data is read and to which data is written; and a memory controller that receives from a host workload items in a workload sequence, each workload item being defined by at least a start logical block address (LBA) and a length. The memory controller merges sequential workload items in the workload sequence to constitute a single workload item; identifies a start workload item for a candidate cluster; stores the LBA and a hit count of the start workload item in a hash table of the memory controller; identifies an end workload item for the candidate cluster; determines whether the candidate cluster is found in the workload sequence more than a threshold number of times; and, if so, accepts the candidate cluster.

Growing community of inventors

Minsk, Belarus

Yauheni Yaromenka