Xilinx, Inc.

Yau-Tsun Steven Li

Dinesh D Gaitonde

Grigor S Gasparyan

Sonal Santan

Stephen P Rozum

Pradip Jha

Sudipto Chakraborty

Sumit Roy

Anup Kumar Sultania

Yenpang Lin

Fei Rui

E Syama Sundara Reddy

Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

Adaptive compilation and execution for hardware acceleration

Designing circuits can include, within a circuit design, detecting, using a processor, a high fan-out net having loads with a same timing requirement, wherein the circuit design is technology specific for a target integrated circuit (IC), determining, using the processor, a region having a predetermined shape and an area sized to fit loads of the high fan-out net within the region on the target IC, and determining, using the processor, a delay of the high fan-out net based upon a distance from a center of the region to an edge of the region. Designing circuits can also include assigning, using the processor, the delay to the high fan-out net.

Delay modeling for high fan-out nets within circuit designs

Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Re-budgeting connections of a circuit design

Processing a circuit design for implementation on a target device includes, for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. The connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

Replicating a driver of a net in a circuit design

Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.

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Cupertino, CA, United States of America

Yau-Tsun Steven Li