Ciena Corporation

Catena Networks, Inc.

Yatish Kumar

Christian Bourget

Fred Stacey

A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.

Flexible buffering scheme for multi-rate SIMD processor

An asymmetric digital subscriber line (ADSL) termination unit, which at the transmission end includes a descrambler and a compressor between its scrambler and interleaver. The present invention provides for the use of compression on the data in a channel to remove some of the inherent redundancy, in order to yield much better throughput, particularly in conjunction with certain powerful forward error correction (FEC) schemes. In this manner the compression may be performed on unscrambled data that has a higher redundancy than scrambled data, thereby improving compression. At the reception end, the ADSL termination unit includes a decompressor and a scrambler between its deinterleaver and descrambler.

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Ottawa, Canada

Yatish Kumar