Intel Corporation

Yatin Hoskote

Sriram R Vangal

Shekhar Yeshwant Borkar

Nitin Y Borkar

Vasantha K Erraguntla

Jianping Xu

Shu-Ling Garver

Vivek K De

Siva G Narendra

Dinesh Somasekhar

Jason M Howard

Amaresh Pangal

Saurabh Dighe

Arvind Pratap Singh

Kiran B Doreswamy

Sriram R Vangai

In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.

Resiliently retaining state information of a many-core processor

Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a scheduler, an on-chip cache, a host memory interface, a host interface, and a network interface controller (NIC) interface. In one embodiment, the TOE is embodied as a memory controller hub (MCH) component of a platform chipset. The TOE may further include an integrated direct memory access (DMA) controller, or the DMA controller may be embodied as separate circuitry on the MCH. In one embodiment, inbound packets are queued in an input buffer, the headers are provided to the scheduler, and the scheduler arbitrates thread execution on the processing engine. Concurrently, DMA payload data transfers are queued and asynchronously performed in a manner that hides memory latencies. In one embodiment, the technique can process typical-size TCP packets at 10 Gbps or greater line speeds.

Hardware-based multi-threading for packet processing

A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel to receive inbound data from the plurality of lanes and to provide outbound data to the plurality of output ports. Each lane may include a local lane arbiter, a global lane arbiter and a port arbiter associated with each port.

Router to use three levels of arbitration for a crossbar channel

A communications receiver includes a digital counter to count transitions of a carrier signal subject to on/off keying.

Communications receiver with digital counter

According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system ('OS') or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.

Reliable computing with a many-core processor

The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).

Network protocol off-load engines

Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.

Network protocol engine

A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. 'Don't care' input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.

System and method for automatically mapping state elements for equivalence verification

Method and apparatus are described for anticipating the number of leading zeros or leading ones in a sum of mantissas irrespective of the sign of the result or the relative magnitudes of the input operands using a leading zero anticipation (LZA) device. An algorithm is presented for leading zero and leading one anticipation that may be used to remove leading zeroes or ones from sums produced in arithmetic units. This algorithm and the design of the combinational logic does not require a comparison of input operands nor does it need two separate counters for leading zeros and leading ones as in most other LZAs. The present invention is especially applicable to redundant format addition.

Leading Zero Anticipatory (LZA) algorithm and logic for high speed arithmetic units

In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.

Packet-based clock signal

The proposed fast single precision floating point accumulator of the present invention uses base 32 computation in an attempt to completely remove the need for a costly 8-bit subtractor in the exponent path as is commonly found in conventional designs. It also replaces the expensive variable shifter in the mantissa path with a constant shifter which significantly reduces the cost of the present invention relative to earlier floating point accumulators. The variable shifter required for base 2 to base 32 conversion has been moved outside the accumulator loop. This approach allows comparison of the two input exponents using a comparator. The mantissas are shifted by constant amount to bring them into partial alignment. They are then added or the appropriate mantissa is chosen as the result. The input stream to the accumulator does not need to be cumulative.

Fast single precision floating point accumulator using base 32 system

An algorithm and implementation is described of overflow prediction for addition without the use of an expensive addition operation. This overflow prediction is particularly applicable to the implementation of addition operation using the carry-save format in high speed arithmetic units.

Overflow prediction algorithm and logic for high speed arithmetic units

A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.

Floating point adder

One aspect of the invention is a coverage metric to identify that part of a state space which is covered by properties verified by model checking. In each property, a signal is identified (or a proposition on several signals) as the observed signal in that property. The coverage metric measures the coverage of a set of properties with respect to the observed signal. The coverage metric identifies the reachable states in which the value of the observed signal determines the validity of the verified properties. Then a model checking algorithm can be used to check the correctness condition on the observed signal in these &ldquo;covered&rdquo; states to prove or disprove the property.

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Portland, OR, United States of America

Yatin Hoskote