Ross Technology Corporation

Yatin G Mundkur

Anantakotiraju Vegesna

Peter H Jewett

Jayachandra B Avula

James E Monaco

Vinay J Naik

Douglas M Carmean

An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.

Processor which performs dynamic instruction scheduling at time of

An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.

CPU architecture performing dynamic instruction scheduling at time of

Central processing unit architecture with symmetric instruction

A method and apparatus for sizing components of an electronic circuit by replacing standard cells representative of the components in the circuit with other standard cells from a standard cell library in order to improve the performance so that the circuit meets certain predetermined user-specified criteria. A computer program implementation ('the sizing system') of this method is described. This implementation receives command line options from the user, builds an internal representation of the external standard cell library, builds a database describing the connectivity of the circuit, computes the capacitance seen at each node in the circuit, and queries the user for additional command options. One such option is for the sizing system to size the circuit, via a heuristic algorithm, by replacing standard cells in the circuit with others from a standard cell library in order to improve the circuit's performance.

Method and apparatus for optimizing electronic circuits

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Austin, TX, United States of America

Yatin G Mundkur