Sanyo Electric Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Other

Panasonic Corporation

Adeia Semiconductor Advanced Technologies Inc.

Yasuyuki Yanase

Yoshio Okayama

Koichi Saito

Tsutomu Kiyosawa

Ryosuke Usui

Tetsuya Yamamoto

Kazuhiro Kagawa

Yasunori Inoue

Takahiro Fujii

Hideki Mizuhara

Mayumi Nakasato

Hajime Kobayashi

Kiyoshi Shibata

Masurao Yoshii

Atsunobu Suzuki

Masao Uchida

Takashi Hasegawa

Haruyuki Sorada

Nobuyuki Horikawa

Yasuhiro Kohara

Masayuki Nagamatsu

Koutarou Tanaka

Kouichi Saitou

A semiconductor element mounted on an insulating resin layer formed on a wiring layer is sealed by a sealing resin. On the wiring layer, a protruding electrode protruding to the side of the semiconductor element and a protruding section are integrally formed with the wiring layer, respectively. The protruding electrode is electrically connected to an element electrode of the semiconductor element by penetrating the insulating resin layer. The protruding section is arranged to surround the semiconductor element along the four sides of the semiconductor element, and is embedded in the sealing resin up to a position above a section where the protruding electrode and the element electrode are bonded.

Semiconductor module and portable apparatus provided with semiconductor module

A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, and a semiconductor layer. The semiconductor layer includes a level difference for alignment mark. An epitaxial layer is disposed on a first portion of the main surface, the first portion being situated on an off-angle upstream side of the level difference, and on a second portion of the main surface, the second portion being situated on an off-angle downstream side of the level difference. A value of |WL&#x2212;WR| is 1 &#x3bc;m or less, in which WL represents a distance from a center of the level difference to a boundary between an off-angle upstream side corner portion of the level difference and a main surface or a {0001} facet plane generated on the main surface, and WR represents a distance from the center of the level difference to a boundary between an off-angle downstream side corner portion of the level difference and the main surface or the {0001} facet plane generated on the main surface.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, a semiconductor layer, and an epitaxial layer. The semiconductor layer includes a trench. Where an upstream side is an off-angle upstream side and a downstream side is an off-angle downstream side in a direction with the off-direction projected on the main surface of the substrate, a side wall of the trench includes first and second side wall portions facing each other and each crossing the off-direction of the substrate. The first side wall portion is situated closer to the off-angle upstream side than the second side wall portion.

Metal-insulator-semiconductor field effect transistor (MISFET) device and method for manufacturing the same

An ohmic electrode layer is disposed on a second main surface of a silicon carbide substrate, and a metal electrode layer is disposed on the ohmic electrode layer. A notch is formed along at least one pair of sides, facing each other, of a periphery of the second main surface of the silicon carbide substrate. The cross-section of the notch orthogonal to a side of the second main surface has a corner. In the cross-section, a thickness of the silicon carbide substrate at an edge thereof under which the notch is formed is smaller than a thickness of the silicon carbide substrate in a region under which the notch is not formed, and larger than a thickness of the silicon carbide substrate in a region under which a bottom of the corner is formed.

Semiconductor element, semiconductor element manufacturing method, semiconductor module, semiconductor module manufacturing method, and semiconductor package

A device mounting board comprises: a heat dissipating substrate formed of a material containing at least one metal material selected from a group including Al, Mg, and Ti; an insulting resin layer laminated on the heat dissipating substrate; and a wiring layer laminated on the insulating resin layer, and on which a power module is to be mounted. The heat dissipating substrate comprises a random porous layer arranged such that it faces the insulating resin layer, and having cavities elongated in respective random directions.

Device mounting board, cell, and battery module

A semiconductor device includes: a substrate with an off-angle; an SiC layer provided on a principal surface of the substrate, including an n type drift region, and having a trench whose bottom is located in the drift region; and a gate electrode provided in the trench in the SiC layer. In the trench in the SiC layer, a first angle formed by at least part of a first sidewall on an off-direction side and the principal surface of the substrate is an obtuse angle, and a second angle formed by at least part of a second sidewall opposite to the first sidewall and the principal surface of the substrate is an acute angle, in a cross section parallel to a direction of a normal line to the principal surface of the substrate and a direction of a c-axis of the substrate.

Semiconductor device and method for manufacturing same

After a microcrystalline layer having a grain size that is finer than that of a base member is formed on the surface of at least one of a first bonding portion and a second bonding portion, the gap between the first bonding portion and the second bonding portion is filled with a solution into which copper oxide can be eluted, so as to deposit copper oxide contained in the surface oxide film into the solution. By applying pressure and by heating at a temperature of at most the copper recrystallization temperature, the components contained in the solution are removed except for copper, so as to elute copper oxide, thereby bonding the first bonding portion and the second bonding portion via the copper thus deposited. Subsequently, the copper is solid-phase diffused into the first bonding portion and the second bonding portion.

Metal bonded structure and metal bonding method

A semiconductor layerhaving a drift region, a body region, and a source regionprovided at a position next to the body region; an epitaxial layerin contact with the body region; and a gate insulating filmprovided on the epitaxial layer are formed on a principal surface of a semiconductor substrate. The epitaxial layer includes an interface epitaxial layerin contact with the body region, a first epitaxial layeron the interface epitaxial layer, and a second epitaxial layeron the first epitaxial layer. An impurity concentration of the interface epitaxial layer is higher than an impurity concentration of the first epitaxial layer, and lower than an impurity concentration of the second epitaxial layer.

Semiconductor device which can withstand high voltage or high current and method for fabricating the same

The gap between first and second bonding portions is filled with a disperse solution obtained by dispersing copper micro-particles into a solution for copper oxide elution, so as to elute copper oxide configured as the outermost layer of the first bonding portion and copper oxide configured as the outermost layer of the second bonding portion, and copper oxide formed on the surface of each copper micro-particle. Pressure is applied to the first and second bonding portions using a press machine so as to raise the pressure of the disperse solution. At the same time, heat is applied under a relatively low temperature condition of 200&#xb0; C. to 300&#xb0; C., so as to remove the components contained in the disperse solution except for copper, thereby depositing copper. Thus, a first base portion and a second base portion are bonded via a copper bonded portion containing copper derived from the copper micro-particles.

Metal bonding method and metal bonded structure

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130&#xb0; C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170&#xb0; C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Method for manufacturing a circuit device

A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes.

Semiconductor module, method for manufacturing semiconductor module, and portable device

An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Semiconductor module, method of manufacturing semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.

Device mounting board and manufacturing method therefor, and semiconductor module

A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

Growing community of inventors

Gifu, Japan

Yasuyuki Yanase