Sony Computer Entertainment Inc.

Yasuyuki Yamamoto

Yuichi Inomata

Hideaki Io

Makoto Tanaka

Masakazu Suzuoki

Makoto Furuhashi

Teiji Yutaka

Masayoshi Tanaka

Toru Akazawa

Toyoshi Okada

Shigekazu Hayashi

Shinichi Fukushima

There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asserted, a timer portionis activated. When the timer portiondetects that the wait signal is kept asserted for more than a predetermined period of time, it asserts a wait mask signal. Upon assertion of the wait mask signal, a mask portionmasks the wait signal from the PC card so that the wait signal to the CPU is negated even when the wait signal is kept asserted. Further, when the timer portionasserts the wait mask signal, an interrupt control block/card status registerasserts an interrupt signal to the CPU.

Interrupt controller in an interface device or information processing system

An entertainment apparatus comprising a peripheral device and a controller for controlling the peripheral device. The peripheral device and the controller are connected each other by an address bus and a data bus. The peripheral device which receives a DMA acknowledge signal from the controller carries out 32-bit DMA transfer using lower 16 bits of the address bus and the data bus, during assertion of the DMA acknowledge signal.

Entertainment apparatus

An entertainment apparatus is configured to enable a program for an older version of the apparatus to be executed. In a normal mode, a main processing unit (MPU) operates as a main CPU, a graphics processor (GP) operates as a graphics processor, and an input/output subprocessor (IOP) operates as a subprocessor for input and output. In a compatible mode in which a program for an older version of the apparatus is executed, the IOP capable of executing the program for the older version of the apparatus operates as a main CPU, and the MPU and GP emulate a graphics processor for the older version of the apparatus.

Entertainment apparatus having compatibility and computer system

In a game system such as a television game system, a television game machine main unit includes a protocol controller and each game operation device connected to the television game machine unit via a serial port also has a protocol controller. The television game machine main unit when connected to a game operation device which has a unique identifier, combines a communication protocol that transmits and receives data for each character with a communication protocol which transmits or receives data for two or more characters in a row and switches the communication protocol which corresponds to that game operation device based on the identifier thereof to minimize the amount of information required between the television game machine main unit and the game operation device.

Game device, game machine operation device and game system which employ a half-duplex serial communication system and game device two-way communication method

A first bus and a second bus are connected through a bus repeater having a buffer memory, and DMA (Direct Memory Access) controllers are respectively connected to the buses and The bus repeater can issue DMA request to the respective DMA controllers and these DMA requests can be masked by respective CPUs The DMA controller carries out DMA transfer of data on the bus between the DMA controller and the buffer memory within the bus repeater and the DMA controller carries out DMA transfer between the buffer memory and the bus The CPU masks DMA request of the bus repeater to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out.

Adding a dummy data or discarding a portion of data in a bus repeater buffer memory for a second data transfer to a second bus

A first bus,and a second bus,are connected through a bus repeater,having a buffer memory, and DMA (Direct Memory Access) controllers,are respectively connected to the buses,and,The bus repeater,can issue DMA request to the respective DMA controllers,and these DMA requests can be masked by respective CPUs,The DMA controller,carries out DMA transfer of data on the bus,between the DMA controller,and the buffer memory within the bus repeater,and the DMA controller,carries out DMA transfer between the buffer memory and the bus,The CPU,masks DMA request of the bus repeater,to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out.

Growing community of inventors

Kawasaki, Japan

Yasuyuki Yamamoto