Kabushiki Kaisha Toshiba

Yasuyuki Onda

Kimio Anai

An image displaying device comprises a display panel including display pixels connected to signal lines signal line driving circuit sections for sampling a video signal including effective video periods and blanking periods between effective video periods to produce pixel signal voltages and supplying the voltages to the signal lines for each of the horizontal scanning lines a drive timing select circuit section for selecting one of a first timing and a second timing in the blanking period of the video signal and a polarity inverting circuit section for inverting the video signal in polarity with respect to a reference voltage on the basis of a selected one of the first and second timing, wherein the drive timing select circuit section is arranged such that each of the first timing and the second timing is selectable when a pixel signal voltage corresponding to the first video signal is obtained from the video signal and outputted to the signal lines for each of the horizontal scanning lines.

Method and apparatus for displaying image

In a liquid crystal display device, an X-driver circuit and a Y-driver circuit are associated with each other to thin out image to be displayed in a display area, under the control of a control circuit. A common electrode drive circuit supplies a common electrode signal to a common electrode under the control of the control circuit. In a canceled scanning period, average-correction is performed to average a polarity inversion time of the common electrode signal for driving the common electrode.

Flat-panel display device and display method

A method of displaying an image on a display screen and a image display device are described. The display device includes a display screen, horizontal and vertical scanning circuits, and a control circuit. The display screen has a predetermined aspect ratio of its lateral axis length and its longitudinal axis length. The horizontal scanning circuits derive signal voltages from a video signal in accordance with a clock signal and provide the same to pixels of horizontal pixel lines. The vertical scanning circuits select the horizontal pixel lines. The control circuit includes a divider circuit to divide a reference clock signal by first and second dividing ratios, and a switching circuit to select either a combination of the reference clock signal and an output signal of the divider circuit by the first dividing ratio or an output of the divider circuit divided by the second dividing ratio so that it may supply the clock signal to the horizontal scanning circuit.

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Miki, Japan

Yasuyuki Onda