Sharp Kabushiki Kaisha Corporation

Yasuyuki Ogawa

Kaoru Yamamoto

Seiichi Uchida

Shigeyasu Mori

Yutaka Takamaru

Kohhei Tanaka

Seiji Kaneko

Tadayoshi Miyamoto

Kazuatsu Ito

Makoto Nakazawa

Mitsunobu Miyamoto

Yutaka Takafuji

Tamotsu Sakai

Takuya Matsuo

Noritaka Kishi

Masanori Ohara

Noboru Noguchi

Shigetsugu Yamanaka

Daichi Nishikawa

Takashi Itoga

Akihiro Oda

Masahiro Tomida

Christopher J Brown

Hiroyuki Ogawa

Kazuhiro Maeda

Mitsuhiro Murata

Yasuhiro Sugita

Kazutoshi Kida

Shinji Yamagishi

Yuhji Yashiro

Osamu Sasaki

Ken Kuboki

Hiroyuki Ohkawa

Akira Shibazaki

Noriaki Yamaguchi

In a current measurement period set in a pause period, a display device of the present invention applies measurement voltages to data lines (Sto Sm) and measures currents outputted to monitoring lines (Mto Mm) from m pixel circuits (), and then applies data voltages generated corresponding to video signals to the data lines (Sto Sm).

Display device and method for driving same

In a forward shift operation, a second input signal having a higher voltage than a voltage of a first input signal is input to a second gate terminal in a case that a first gate terminal of a first transistor is charged, and a fourth input signal having a higher voltage than a voltage of a third input signal is input to a third gate terminal in a case that the first gate terminal of the first transistor is discharged. In a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

Unit shift register circuit, shift register circuit, control method for unit shift register circuit, and display device

A shift register circuit can achieve high definition of a display device with the smallest possible number of elements without causing defective operation. A unit circuit is provided with a thin film transistor functioning as an output control transistor; a thin film transistor precharging an internal node based on an on-level signal outputted from an output terminal of a previous stage; two thin film transistors provided in series with each other between the output terminal of the previous stage and the internal node of this stage; a thin film transistor provided between the internal node and an output terminal; and a thin film transistor pulling down the output terminal. The thin film transistors go to an on state only for a quarter period of a clock cycle which is a part of a period during which the output terminal of the previous stage is pulled down.

Shift register circuit and display device provided with same

A unit shift register circuit constitutes each stage of a shift register circuit. The unit shift register circuit includes an output transistor (T) configured to input a prescribed clock signal (CK) to a drain terminal, and output an output signal (OUT) from a source terminal. The unit shift register circuit includes a setting transistor (T) in which a source terminal is connected to a gate electrode of the output transistor (T), is configured to input an input signal (S) to the drain terminal, and is configured to input to a gate electrode an input signal (VS) in a case of charging a gate electrode (node (VC)) of the output transistor (T). The input signal (VS) having a voltage higher than that of the input signal (S).

Unit shift register circuit, shift register circuit, method for controlling unit shift register circuit, and display device

A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.

Display device and driving method thereof

A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.

Shift register circuit, drive circuit, and display device

At the time of partial drive, the levels of voltages applied to data lines SL1 to SLn are switched according to a rewrite frequency set for each region of a display screen. For example, in a still-image display region with a relatively low rewrite frequency, the levels of the voltages applied to the data lines SL1 to SLn are set to be higher than those for a moving-image display region with a relatively high rewrite frequency. By this, the same effect as that obtained when a counter voltage is switched according to the rewrite frequency can be obtained. Thus, flicker occurring in each region of the display screen can be suppressed.

Liquid crystal display device and method for driving the same

In a display control circuit () of a display device, an image pattern detection portion () detects whether an image is an anti-flicker pattern or not, and when it is an anti-flicker pattern, a backlight source is driven (typically, such that its luminance changes in the opposite phase relative to luminance changes that would occur), on the basis of predicted values, which are predetermined so as to compensate for the luminance changes that would occur. Moreover, the backlight is not turned on during the scanning period. As a result, flicker due to current leakage, etc., can be reduced or eliminated in a display device for which a scanning period and a scan stop period are set.

Display device with compensating backlight drive circuit and method for driving same

A semiconductor device (A) includes a substrate (), an oxide semiconductor layer () formed on the substrate (), source and drain electrodes () electrically connected to the oxide semiconductor layer (), a first transparent electrode () electrically connected to the drain electrode (), a dielectric layer () formed on the source and drain electrodes (), and a second transparent electrode () formed on the dielectric layer (). The upper and/or lower surface(s) of the first transparent electrode () contacts with a reducing insulating layer () with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (). The second transparent electrode () overlaps at least partially with the first transparent electrode () via the dielectric layer (). The oxide semiconductor layer () and the first transparent electrode () are formed out of the same oxide film.

Semiconductor device and method for producing same

This semiconductor device (A) includes: a substrate (); a gate electrode () formed on the substrate (); a gate insulating layer () formed over the gate electrode (); an oxide semiconductor layer () formed on the gate insulating layer (); source and drain electrodes () electrically connected to the oxide semiconductor layer (); a first transparent electrode () electrically connected to the drain electrode (); an interlayer insulating layer () including portions formed on the source and drain electrodes (); and a second transparent electrode () formed on the interlayer insulating layer (). At least a portion of the second transparent electrode () overlaps with the first transparent electrode () with the interlayer insulating layer () interposed between them. And the oxide semiconductor layer () and the first transparent electrode () are formed out of a same oxide film.

This semiconductor device (A) includes: an oxide layer () which includes a semiconductor region () and a conductor region () that contacts with the semiconductor region; a source electrode () and a drain electrode () which are electrically connected to the semiconductor region; an insulating layer () formed on the source and drain electrodes; a transparent electrode () arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line () formed out of the same conductive film as the source electrode; and a gate extended line () formed out of the same conductive film as a gate electrode (). The source line is electrically connected to the gate extended line via a transparent connecting layer () which is formed out of the same conductive film as the transparent electrode.

Semiconductor device and method of manufacture thereof

The TFT substrate () of this liquid crystal display device () includes: a TFT () which is provided for each pixel; an upper electrode () which is electrically connected to the TFT's drain electrode (); a lower electrode () which is arranged under the upper electrode; and a dielectric layer () which is arranged between the upper and lower electrodes. Its counter substrate () includes a counter electrode () which faces the upper electrode. The upper electrode has first and second regions (R, R) which have mutually different electrode structures, and a third region (R) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion () that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L) that splits each pixel into two adjacent regions in a row direction.

Liquid-crystal display apparatus with large viewing angle and high optical transmittance

Provided is a liquid crystal display device with reduced power consumption employing a CS drive method. A CS driver () consists of a CS shift register () and a CS output portion (). The CS shift register () outputs control signals (COUT() to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion () outputs auxiliary capacitance signals (CSS() to CSS(m)) in accordance with the control signals (COUT() to COUT(m)), respectively. An idle period (T) is set following a scanning period (T). During the idle period (T), the CS driver () is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck). The idle-period CS frequency (fcck) is lower than a scanning-period CS frequency (fcck).

Liquid crystal display device and method for driving auxiliary capacitance lines

This semiconductor device () includes: a gate electrode (); a gate insulating layer (); an oxide layer () which is formed on the gate insulating layer () and which includes a first conductor region () and a first semiconductor region () that overlaps at least partially with the gate electrode () with the gate insulating layer () interposed between them; a source electrode () formed to contact with the upper surface of the first semiconductor region () of the oxide layer (); a drain electrode () which is formed to contact with the upper surface of the first semiconductor region () of the oxide layer () and which is electrically connected to the first conductor region (); and a conductive layer () which is formed in contact with the upper surface of the oxide layer () and which a plurality of holes () or notches. The oxide layer () has a plurality of second conductor regions (), and each of which has a surface exposed inside respective one of the holes or notches of the conductive layer.

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Osaka, Japan

Yasuyuki Ogawa