Renesas Electronics Corporation

Nec Electronics Corporation

Nec Corporation

Idemitsu Kosan Company, Limited

Sds Biotech K.k.

Yasuyuki Morishita

Masanori Tanaka

Osamu Kato

Satoshi Maeda

Takanori Eguchi

Morihisa Hirata

Keijitsu Tanaka

Yusuke Amaki

Mutsumi Miyazaki

Yuki Tsukagoshi

Yoshihito Uzawa

A semiconductor device includes an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit arranged on a chip, and the core power supply cell includes an ESD protection circuit. The input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell. The core logic circuit is arranged outside the input/output cell. The core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged.

Semiconductor device

A semiconductor device includes a protection element configured by a MOSFET, and the protection element has a multilayer metal wiring structure. The multilayer metal wiring structure includes drain connection wirings connected to drain regions of the MOSFET and source connection wirings connected to source regions of the MOSFET. In a part of a layer of the multilayer metal wiring structure where both the drain connection wirings and the source connection wirings are present, only either the drain connection wirings or the source connection wirings are laid out in a grained pattern.

A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.

An object of the present invention is to provide a novel culturing method by which spores can be efficiently produced. The present invention further provides a method for culturing sporulating bacteria, comprising adding a sporulation-inhibiting substance into a medium for culturing sporulating bacteria, wherein the carbon content in the medium is 9.1 g/L or more, and preferably further comprising a step of adding a sporulation-accelerating substance to the medium.

Method for culturing spore-forming bacteria, and method for producing useful substance

The present invention provides a method for producing bacterial cells, which comprises, in a multi-stage liquid culture process for bacteria, culturing a bacterium in a liquid medium containing an antibiotic in a stage prior to the final stage, and then lowering the concentration of the antibiotic in the final stage to a level lower than that in the prior stage. Accordingly, bacterial cells can be produced with good productivity while suppressing the appearance of variants forming abnormal colonies among the bacteria obtained after culture.

Production method for bacterial cells

A semiconductor device including a digital circuit, a first ground potential line provided corresponding to the digital circuit, an analog circuit, a second ground potential line respectively provided corresponding to the analog circuit, and a bidirectional diode group provided between the first ground potential line and the second ground potential line.

A method of producingspores comprising a step of culturing thebacterium using a liquid medium having a C/N ratio (weight ratio of carbon content to nitrogen content) of greater than 4 and less than 9.5.

Sporulation method ofbacterium

A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.

A semiconductor device that can have both noise resistance and ESD resistance is provided. The semiconductor device includes a first and a second digital circuits, a first and a second ground potential lines respectively provided corresponding to the first and the second digital circuits, a first and a second analog circuits, a third and a fourth ground potential lines respectively provided corresponding to the first and the second analog circuits, a first bidirectional diode group provided between the first and the second ground potential lines, a second bidirectional diode group provided between the third and the fourth ground potential lines, and a third bidirectional diode group provided between the first and the third ground potential lines. The number of stages of bidirectional diodes of the third bidirectional diode group is greater than that included in each of the first and the second bidirectional diode groups.

A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static electricity and a diode which is coupled between a back gate of the MOS transistor and one of the terminal and has a polarity which is reversed to the polarity of a parasitic diode which is formed between the back gate and a source of the MOS transistor.

The present invention relates to a microbial pesticide composition, which is obtained by a method including the steps of: adjusting a pH of a culture solution of thesp. bacterium to from 3.0 to 5.0 (pH adjustment step); mixing the culture solution with the calcium chloride and/or the magnesium sulfate (mixing step); and lyophilizing or spray-drying the culture solution (drying step). In the microbial pesticide composition, even if it is stored for a long period of time at room temperature, the active ingredient remains stable and a sufficient preventive effect against plant disease can be maintained.

[object Object]

An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region.

Semiconductor electrostatic protection circuit device

It is desired to achieve a high ESD protection performance by a small area circuit. An electrostatic discharge protection circuit includes: protection circuits, wherein each protection circuit includes a MOS transistor; and a trigger circuit configured to supply a trigger signal to a gate electrode of the MOS transistor of each protection circuit in response to a surge voltage between a low potential node and a high potential node. Each protection circuit is configured to electrically connect the low potential node and the high potential node to one another when the trigger signal is supplied to the gate electrode. The gate electrode of each protection circuit is connected to a resistive element having larger resistance value than Rmax, supposing that Rmax is a largest parasitic resistance between each of the plurality of protection circuit and an output of the trigger circuit.

Electrostatic discharge protection circuit

A semiconductor circuit includes, a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the third pad and the second pad; and a transistor functioning as a trigger element for use in flowing a trigger current to the protection element. The transistor includes a gate and a backgate being connected to the first pad and is connected to the protection element such that a source potential of the transistor becomes lower than a potential of the third pad, based on a voltage drop caused by the protection element, when potentials of the first pad and the third pad are kept at a power supply voltage level.

Growing community of inventors

Tokyo, Japan

Yasuyuki Morishita