Taiyo Yuden Co., Ltd.

Taiyo Yudenco., Ltd.

Tamura Electric Works, Ltd.

Taiyo Yudan Co., Ltd

Yasuyuki Inomata

Tetsuo Shimura

Yoshiyuki Watanabe

Hiroshi Kishi

Hirokazu Chazono

Shigeo Ishii

Youichi Mizuno

Masaki Mochigi

Kazumi Kaneda

Tomoya Hagiwara

Toshikazu Toba

Kazuyuki Shibuya

Mikio Tahara

Katsuyuki Horie

Osamu Kai

Kazumichi Hiroi

Yoshikazu Okino

Yousuke Nakada

Yasuhisa Kono

Mina Amano

Yosuke Nakada

Toshiharu Morihisa

Mitsuya Tsujikawa

Shintaro Hayashi

A ceramic electronic device includes a dielectric layer and an internal electrode layer that are alternately stacked, wherein the dielectric layer contains yttria-stabilized zirconia, and wherein an arca ratio of grains of the yttria-stabilized zirconia is 1% or more and 15% or less in a cross section of the dielectric layer.

Ceramic electronic device including dielectric layer containing perovskite compound with yttria-stabilized zirconia

A multilayer ceramic electronic device includes a multilayer chip having a plurality of dielectric layers and a plurality of internal electrode layers, one end of each of the plurality of internal electrode layers being exposed from the multilayer chip, an external electrode that is provided on an end face of the multilayer chip and is electrically connected to the one end of at least some of the plurality of internal electrode layers and includes a glass component, the end face being an end of the multilayer chip in a direction in which the plurality of internal electrode layers extend. The external electrode includes a crystal contacting or extending into the glass component at an interface between the external electrode and the end face of the multilayer chip. The crystal includes an element that is the same as at least one of elements included in the plurality of dielectric layers.

Multilayer ceramic electronic device, circuit substrate and manufacturing method of multilayer ceramic electronic device

A ceramic electronic device includes a dielectric layer and an internal electrode layer that are alternately stacked. The dielectric layer contains ceria zirconia solid solution and (CaBaSr)(TiZr)O(0.6≤x≤0.9, 0≤x≤0.1, 0≤y≤0.1) as a main component. In the dielectric layer, a concentration of the ceria zirconia solid solution is 0.5 mol % or more and 5.0 mol % or less when (CaBaSr)(TiZr)Ois 100 mol %.

Ceramic electronic device, dielectric material, and manufacturing method of ceramic electronic device

A ceramic electronic device includes a dielectric layer and an internal electrode layer that are alternately stacked, wherein the dielectric layer contains yttria-stabilized zirconia and (CaBaSr)(TiZr)O(0.6≤x1≤0.9, 0≤x2≤0.1, 0≤y≤0.1) as a main component, and wherein, in the dielectric layer, a concentration of the yttria-stabilized zirconia when a total amount of Ti and Zr is 100 mol % is 0.5 mol % or more and 5.0 mol % or less.

Ceramic electronic device including dielectric layer containing perovskite compound with yttria-stabilized zirconia, and manufacturing method of same

A ceramic electronic device includes a multilayer structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked. Each of the plurality of dielectric layers includes ceramic grains of a main component thereof expressed by (BaCaSr)(TiZr)O(0<x≤0.2, 0≤y≤0.1, 0≤z≤0.1). D3<D1<D2 is satisfied when an average grain diameter of the ceramic grains of the main component of the plurality of dielectric layers in a section in which each two internal electrode layers is D1, an average grain diameter of the ceramic grains of the main component of first dielectric layers which are located at different height positions from the internal electrode layers is D2, an average grain diameter of the ceramic grains of the main component of second dielectric layers which are located at same height positions of the internal electrode layers is D3.

Ceramic electronic device and manufacturing method of the same

A multilayer ceramic capacitor () has a laminate body () constituted by dielectric layers () and internal electrode layers () stacked alternately. The dielectric layers () contain (BaCaSr)(TiZr)O, where 0.03&#x2264;x&#x2264;0.16, 0&#x2264;y&#x2264;0.02, 0&#x3c;z&#x2264;0.02, 0.99&#x2264;m&#x2264;1.02, as a primary component, and an R oxide (R is a rare earth element) by 1.0 to 4.0 mol in equivalent element, an Mg compound by 0.2 to 2.5 mol in equivalent element, an Mn compound by 0.1 to 1.0 mol in equivalent element, a Zr compound by 0.1 to 2.0 mol in equivalent element, a V compound by 0.05 to 0.3 mol in equivalent element, and an Si compound by 0.2 to 5.0 mol in equivalent element, per 100 mol of the primary component. The multilayer ceramic capacitor can offer excellent DC bias properties and ensure high reliability.

Multilayer ceramic capacitor and manufacturing method for same

A multilayer ceramic capacitor includes a laminated body in which dielectric layers and internal electrodes are laminated alternately. The dielectric layer includes a first phase that contains calcium strontium zirconate titanate as a main component thereof and a second phase that contains barium zirconate as a main component thereof. At a cross section of the dielectric layer, a line parallel to the direction in which the dielectric layers and the internal electrodes are laminated contacts the boundaries between the first phase and the second phase once or more on average, thereby the statistically averaged contact number N of such a line with the boundaries determined by a prescribed procedure being 1.0 or greater.

Multilayer ceramic capacitor and manufacturing method therefor

A ceramic electronic device includes a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, wherein a main component of the dielectric layers is (Ba, Sr, Ca)(Zr, Ti)O, wherein a Ba concentration and a Ca concentration have variation in at least one of crystal grains in the dielectric layers.

A ceramic capacitor includes a multilayer structure, wherein a main component of dielectric layers is ceramic expressed by a general formula ABO(0.995&#x2264;m&#x2264;1.010), wherein the dielectric layers include a rare earth element Re as a first sub-component by 2.0 mol to 5.0 mol when converted into ReO/2, include Mg as a second sub-component by 1.0 mol to 3.0 mol when converted into MgO, include V as a third sub-component by 0.05 mol to 0.25 mol when converted into VO/2, include Si as a fourth sub-component by 0.5 mol to 5.0 mol when converted into SiO, include an alkali earth metal element M as a fifth sub-component by 0.1 mol to 5.0 mol when converted into MCO, on a presumption that an amount of the ceramic is 100 mol, wherein a ratio Si/V is 30 or less.

Ceramic capacitor, circuit substrate and manufacturing method of ceramic capacitor

A ceramic capacitor includes: a dielectric layer of which a main component is a ceramic grain, wherein one or more pores are formed inside of the ceramic grains; and wherein an area ratio of the one or more pores with respect to a cross section of the ceramic grain is 0.03% to 0.20%, in a cross section of the dielectric layer.

Ceramic capacitor and manufacturing method thereof

The present technology provides an electronic component with an interposer, including an electronic component and an interposer. An adhesive section is disposed in an opposing space between a main body of the electronic component and a substrate. When a direction in which first and second external electrodes of the electronic component face each other is a first direction, a direction orthogonal to the first direction is a second direction, and a direction in which the electronic component and the interposer face each other is a third direction, the adhesive section includes a plurality of unitary adhesive sections separated from each other, and the unitary adhesive sections are disposed in a two-dimensional array such that the number of unitary adhesive sections arrayed along the second direction is smaller on opposing sides in the first direction than at a center.

Electronic component with interposer

A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, wherein 1.5&#x2264;Db/Da&#x2264;10.0 is satisfied in a side margin region that covers edge portions to which the plurality of internal electrode layers extend toward two side faces other than the first edge face and the second edge face, when Da is an average grain diameter of a main component ceramic within 20 &#x3bc;m from an edge of the plurality of internal electrode layers in the side margin region and Db is an average grain diameter of a main component ceramic within 20 &#x3bc;m from a surface layer of the side margin region.

Multilayer ceramic capacitor and manufacturing method thereof

A multilayer ceramic capacitor includes a multilayer structure wherein [t&#xd7;L]/N&#x2265;10, when a distance between a first edge that is an outermost edge of internal electrodes that is not connected to a first or second external electrode and a second edge that is an innermost edge of the internal electrodes that is not connected to the first or second external electrode is L, each thickness of dielectric layers is t, and a stack number of dielectric layers is N, wherein [t&#xd7;W]/N&#x2265;10, when a distance between a first edge that is positioned at outermost of the internal electrodes and a second edge that is positioned at innermost of the internal electrodes is W, and wherein R is larger than W, when a curvature radius of a corner of an edge of the internal electrodes is R.

Multilayer ceramic capacitor

A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces thereof; and external electrodes formed on the two edge faces; wherein: the external electrodes have a structure in which a plated layer is formed on a ground layer whose main component is a metal or an alloy, a thermal expansion coefficient of the metal being larger than that of a main ceramic component of the dielectric layer, the ground layer including a ceramic additive; outermost layers of the multilayer chip are cover layers whose main component is a main component of the dielectric layer; and thermal expansion coefficients satisfy a relationship of, the main component of the ground layer&#x3e;the main component of the cover layers&#x3e;the ceramic additive.

Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor

In an embodiment, a multilayer ceramic capacitoris constituted in such a way that four capacitive components Cto Cthat are connected in series are formed between a first internal electrode layer groupand a second internal electrode layer groupadjacent to it, wherein, among the four capacitive components Cto C, the facing area Scthat defines the capacitance value of the capacitive component Cclosest to the first external electrodeand the facing area Scthat defines the capacitance value of the capacitive component Cclosest to the second external electrodeare greater than the facing areas Scand Scthat define the capacitance values of the two remaining capacitive components Cand C, respectively. The multilayer ceramic capacitor is capable of satisfying the needs for both size reduction and voltage resistance increase.

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Tokyo, Japan

Yasuyuki Inomata